Five-inputs single-output voltage mode universal filter with high input and low output impedance using VDDDAs

Optik ◽  
2017 ◽  
Vol 128 ◽  
pp. 14-25 ◽  
Author(s):  
Surasak Sangyaem ◽  
Surapong Siripongdee ◽  
Winai Jaikla ◽  
Fabian Khateb
2005 ◽  
Vol 14 (01) ◽  
pp. 159-164 ◽  
Author(s):  
SUDHANSHU MAHESHWARI ◽  
IQBAL A. KHAN

A novel voltage-mode universal filter employing only two current differencing buffered amplifiers (CDBAs) is proposed. The filter uses four inputs and single output to realize six responses, viz. low-pass, high-pass, inverting band-pass, noninverting band-pass, band-elimination, and all-pass through input selection with independent pole-Q control. Computer simulation results using SPICE are also given to verify the theory.


2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Sudhanshu Maheshwari ◽  
Bhartendu Chaturvedi

This paper presents some additional high input low output impedance analog networks realized using a recently introduced single Dual-X Current Conveyor with buffered output. The new circuits encompass several all-pass sections of first- and second-order. The voltage-mode proposals benefit from high input impedance and low output impedance. Nonideality and sensitivity analysis is also performed. The circuit performances are depicted through PSPICE simulations, which show good agreement with theory.


2014 ◽  
Vol 68 (12) ◽  
pp. 1239-1246 ◽  
Author(s):  
Wilas Ninsraku ◽  
Dalibor Biolek ◽  
Winai Jaikla ◽  
Surapong Siripongdee ◽  
Peerawut Suwanjan

2013 ◽  
Vol 22 (01) ◽  
pp. 1250065 ◽  
Author(s):  
SUDHANSHU MAHESHWARI ◽  
JITENDRA MOHAN ◽  
DURG SINGH CHAUHAN

This paper presents two new first-order voltage-mode (VM) cascadable all-pass (AP) sections, employing two differential voltage current conveyors (DVCCs) and three grounded passive components. Both circuits possess high input and low output impedance, which makes them easily cascadable. Non-ideality aspects and parasitic effects are also studied. As an application, a quadrature oscillator is designed using the proposed circuit. The proposed circuits are verified through PSPICE simulations using 0.5 μm CMOS parameters.


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