In this paper the strain effects on the performance and reliability of future digital III-V device are discussed. Strain is incorporated in the device during fabrication, packaging, and operation. A high amount of strain can introduce defects and cracks in the epilayer. The band structure of the active device region is also altered due to strain. These strain induced changes determine performance, reliability, and lifetime of the device. Therefore, it is necessary to consider strain effects while designing a device for a particular application. Here, compressive-strain-induced changes are used as design parameters and their impact on the logic performance of the device is studied. It is interpreted that the design significantly decreases the gate leakage current and improves the subthreshold slope.