Optimal design towards enhancement of board-level thermomechanical reliability of wafer-level chip-scale packages

Microelectronics Reliability ◽

10.1016/j.microrel.2006.04.008 ◽

2007 ◽

Vol 47 (1) ◽

pp. 104-110 ◽

Author(s):

Yi-Shao Lai ◽

Tong Hong Wang

Keyword(s):

Optimal Design ◽

Wafer Level ◽

Thermomechanical Reliability ◽

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Optimal design of dummy ball array in wafer level package to improve board level thermal cycle reliability (BLR)

2018 IEEE International Reliability Physics Symposium (IRPS) ◽

10.1109/irps.2018.8353653 ◽

2018 ◽

Author(s):

Seongwon Jeong ◽

Jinseok Kim ◽

Ayoung Kim ◽

Byungwook Kim ◽

Moonsoo Lee ◽

...

Keyword(s):

Optimal Design ◽

Thermal Cycle ◽

Wafer Level ◽

Board Level ◽

Wafer Level Package

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Low stress dielectric layers for wafer level packages to reduce wafer warpage and improve board-level temperature-cycle reliability

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC) ◽

10.1109/eptc.2016.7861466 ◽

2016 ◽

Author(s):

James T. Huneke ◽

SweeTeck Tay

Keyword(s):

Temperature Cycle ◽

Wafer Level ◽

Dielectric Layers ◽

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Structural design optimization for board-level drop reliability of wafer-level chip-scale packages

Microelectronics Reliability ◽

10.1016/j.microrel.2008.01.003 ◽

2008 ◽

Vol 48 (5) ◽

pp. 757-762 ◽

Author(s):

Tsung-Yueh Tsai ◽

Yi-Shao Lai ◽

Chang-Lin Yeh ◽

Rong-Sheng Chen

Keyword(s):

Design Optimization ◽

Structural Design ◽

Wafer Level ◽

Structural Design Optimization ◽

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Package & board level reliability study of 0.35mm fine pitch wafer level package

2017 18th International Conference on Electronic Packaging Technology (ICEPT) ◽

10.1109/icept.2017.8046464 ◽

2017 ◽

Author(s):

Peng Sun ◽

Jun Liu ◽

Cheng Xu ◽

Liqiang Cao

Keyword(s):

Wafer Level ◽

Reliability Study ◽

Board Level ◽

Wafer Level Package ◽

Board Level Reliability

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Modeling techniques for board level drop test for a wafer-level package

2008 International Conference on Electronic Packaging Technology & High Density Packaging ◽

10.1109/icept.2008.4607141 ◽

2008 ◽

Author(s):

Harpreet S. Dhiman ◽

Xuejun Fan ◽

Tiao Zhou

Keyword(s):

Drop Test ◽

Wafer Level ◽

Modeling Techniques ◽

Board Level ◽

Wafer Level Package

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Board level reliability enhancements for wafer level package

2015 Annual Reliability and Maintainability Symposium (RAMS) ◽

10.1109/rams.2015.7105070 ◽

2015 ◽

Author(s):

John Qiao ◽

Wenwen He ◽

Kelly Yang ◽

Wei-Ting Kary Chien

Keyword(s):

Wafer Level ◽

Board Level ◽

Wafer Level Package ◽

Board Level Reliability

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Reliability investigations of large die wafer level package (part II): Impact of solder ball composition, die thickness, and polymer passivition on board level reliability

2016 6th Electronic System-Integration Technology Conference (ESTC) ◽

10.1109/estc.2016.7764492 ◽

2016 ◽

Author(s):

Chien-An Hsieh ◽

Markus Jarn ◽

Yu-Chi Pai ◽

Yi-Liang Chen ◽

Bradford J. Factor ◽

...

Keyword(s):

Solder Ball ◽

Wafer Level ◽

Board Level ◽

Wafer Level Package ◽

Board Level Reliability ◽

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Studying the Effect of Stackup Structure of Large Die Size Fan-In Wafer Level Package at 0.35 mm Pitch With Varying Ball Alloy to Enhance Board Level Reliability Performance

2016 IEEE 66th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2016.17 ◽

2016 ◽

Author(s):

Kuei Hsiao Kuo ◽

Jerry Chiang ◽

Kui Chang ◽

Jack Shu ◽

F. L. Chien ◽

...

Keyword(s):

Wafer Level ◽

Reliability Performance ◽

Board Level ◽

Wafer Level Package ◽

Board Level Reliability

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Board Level Reliability Study of Next Generation Large Die Wafer Level Chip Scale Package Structures

2018 International Wafer Level Packaging Conference (IWLPC) ◽

10.23919/iwlpc.2018.8573297 ◽

2018 ◽

Author(s):

Timo Henttonen ◽

Paul Mescher ◽

Doug Scott ◽

Han Park ◽

YongJae Ko ◽

...

Keyword(s):

Next Generation ◽

Wafer Level ◽

Reliability Study ◽

Chip Scale Package ◽

Board Level ◽

Board Level Reliability

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Thermomechanical reliability of Large Wafer Level Chip Scale Packages (LWLCSP) under thermal cycling qualification test

2018 7th Electronic System-Integration Technology Conference (ESTC) ◽

10.1109/estc.2018.8546423 ◽

2018 ◽

Author(s):

Balaji Nandhivaram Muthuraman ◽

Baltazar Canete

Keyword(s):

Thermal Cycling ◽

Qualification Test ◽

Wafer Level ◽

Thermomechanical Reliability

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