Low stress dielectric layers for wafer level packages to reduce wafer warpage and improve board-level temperature-cycle reliability

Wafer level chip scale packages (WLCSP) have been increasingly used in portable electronic products such as mobile phones. Solder bumps with redistribution layer (RDL) are typical interconnect technology for WLCSP applications. One of the major concerns in joint reliability is the failure by temperature cyclic stresses. In addition, in terms of heat tolerance or device yields, process temperature of RDL dielectric is limited around 200deg.C in some packaging applications. According to our board level reliability test for temperature cycle test (TCT), photosensitive polyimide (PI) which is 200deg.C curable material has lower fail rate than polybenzoxazole (PBO) by TCT. In this study, we compared the actual board level test and Finite Element Analysis (FEA) during temperature cycle test, and correlated the mechanical and fatigue properties of passivation layer material with TCT reliability.

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Revealing Metal Corrosion Failures Using Wafer Level Temperature Cycle Stress Testing

10.1109/irws.1993.666312 ◽

2005 ◽

Author(s):

J.M. Duffalo ◽

J.E. Staszkow ◽

J.A. Chan ◽

P.D. Egelhoff ◽

H.A. Pollack ◽

...

Keyword(s):

Stress Testing ◽

Metal Corrosion ◽

Temperature Cycle ◽

Wafer Level

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Structural design optimization for board-level drop reliability of wafer-level chip-scale packages

Microelectronics Reliability ◽

10.1016/j.microrel.2008.01.003 ◽

2008 ◽

Vol 48 (5) ◽

pp. 757-762 ◽

Cited By ~ 15

Author(s):

Tsung-Yueh Tsai ◽

Yi-Shao Lai ◽

Chang-Lin Yeh ◽

Rong-Sheng Chen

Keyword(s):

Design Optimization ◽

Structural Design ◽

Wafer Level ◽

Structural Design Optimization ◽

Board Level

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Robust Reliability Performance of Large size eWLB (Fan-out WLP)

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2013dpc-wp21 ◽

2013 ◽

Vol 2013 (DPC) ◽

pp. 001438-001457 ◽

Cited By ~ 4

Author(s):

Seung Wook Yoon

Keyword(s):

Form Factor ◽

Dielectric Materials ◽

Structural Defects ◽

Temperature Cycle ◽

Wafer Level ◽

Component Level ◽

Wafer Level Packaging ◽

Large Size ◽

Reliability Performance ◽

Robust Reliability

With reducing form-factor and functional integration of mobile devices, Wafer Level Packaging (WLP) is attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP, it is more optimal and promising solution compared to fan-in WLP, because it can offer greater flexibility in design of more IOs, multi-chips, heterogeneous integration and 3D SiP. eWLB (embedded wafer level packaging) is a type of fan-out WLP enabling applications that require smaller form-factor, excellent heat dissipations, thin package profile as it has the potential to evolve in various configurations with proven manufacturing capacity and production yield. This paper discusses the recent advancements of robust reliability performance of large size eWLB. It will also highlight the recent achievement of enhanced component level reliability with advanced dielectric materials. After a parametric study and mechanical simulations, new advanced materials were selected and applied to eWLB. Standard JEDEC tests were carried out to investigate component level reliability of large size (9x9~14x14mm2) test vehicles and both destructive/non-destructive analysis were performed to investigate potential structural defects. Daisychain test vehicles were also tested for drop and TCoB (Temperature Cycle on Board) reliability performance in industry standard test conditions. Besides, this paper will also present a study of package level warpage behaviour with Thermo-Moire measurement.

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Mechanical and Thermal Board Level Reliability Comparison Between Electroless Ni Im. Au and Solder on Pad Surface Finishes for Large Flip Chip BGA Packages

Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology ◽

10.1115/imece2006-16074 ◽

2006 ◽

Author(s):

Gnyaneshwar Ramakrishna ◽

Donghyun Kim ◽

Mudasir Ahamad ◽

Lavanya Gopalakrishnan ◽

Mason Hu ◽

...

Keyword(s):

Surface Finish ◽

Flip Chip ◽

High Reliability ◽

Electroless Nickel ◽

Temperature Cycling ◽

Design Parameters ◽

Temperature Cycle ◽

Bga Packages ◽

Reliability And Robustness ◽

Board Level

Large Flip Chip BGA (FCBGA) packages are needed in high pin out applications (>1800), e.g., ASIC's and are typically used in high reliability and robustness applications. Hence understanding the package reliability and robustness becomes one of paramount importance for efficient product design. There are various aspects to the package that need to be understood, to ensure an effective design. The focus of this paper is to understand the BGA reliability of the package with particular reference to comparison of the surface finish, vis-a`-vis, between Electroless Nickel Immersion Gold (ENIG) and Solder On Pad (SOP) on the substrate side of the package, which are the typical solutions for large plastic FC-BGA packages. Tests, which include board level temperature cycling, monotonic bend and shock testing have been conducted to compare the two surface finish options. The results of these tests demonstrate that the mechanical strength of the interface exceeds by a factor of two for the SOP surface finish, while BGA design parameters play a key role in ensuring comparative temperature cycle reliability in comparison with ENIG packages.

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