Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

Physica E Low-dimensional Systems and Nanostructures ◽

10.1016/j.physe.2016.04.017 ◽

2016 ◽

Vol 83 ◽

pp. 95-100 ◽

Author(s):

J. Charles Pravin ◽

D. Nirmal ◽

P. Prajoon ◽

J. Ajayan

Keyword(s):

Low Power ◽

High K ◽

Nanowire Mosfet ◽

Nanoscale Circuits

Download Full-text

A high-k, metal gate vertical-slit FET for ultra-low power and high-speed applications

2015 Annual IEEE India Conference (INDICON) ◽

10.1109/indicon.2015.7443732 ◽

2015 ◽

Author(s):

Somesh Kumar ◽

Sarabjeet Kaur ◽

Rohit Sharma

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Vertical Slit ◽

Download Full-text

32nm gate-first high-k/metal-gate technology for high performance low power applications

2008 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2008.4796770 ◽

2008 ◽

Author(s):

C. H. Diaz ◽

K. Goto ◽

H.T. Huang ◽

Yuri Yasuda ◽

C.P. Tsao ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Download Full-text

Scaling of 32nm low power SRAM with high-K metal gate

2008 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2008.4796660 ◽

2008 ◽

Author(s):

H. S. Yang ◽

R. Wong ◽

R. Hasumi ◽

Y. Gao ◽

N.S. Kim ◽

...

Keyword(s):

Low Power ◽

Download Full-text

CMOS Compatible Dual Metal Gate Integration with Successful Vth Adjustment on High-k HfTaON by High-Temperature Metal Intermixing

2006 European Solid-State Device Research Conference ◽

10.1109/essder.2006.307661 ◽

2006 ◽

Author(s):

C. Ren ◽

D. H. Chan ◽

W. Loh ◽

J. Peng ◽

S. Balakumar ◽

...

Keyword(s):

High Temperature ◽

High K ◽

Cmos Compatible ◽

Download Full-text

A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

2009 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm.2009.5424258 ◽

2009 ◽

Author(s):

C.-H. Jan ◽

M. Agostinelli ◽

M. Buehler ◽

Z.-P. Chen ◽

S.-J. Choi ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

High Density ◽

Ultra Low Power ◽

High K ◽

Platform Technology

Download Full-text

Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

2009 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm.2009.5424251 ◽

2009 ◽

Author(s):

C. Fenouillet-Beranger ◽

P. Perreau ◽

L. Pham-Nguyen ◽

S. Denorme ◽

F. Andrieu ◽

...

Keyword(s):

Low Power ◽

Multimedia Technology ◽

Download Full-text

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

2012 International Electron Devices Meeting ◽

10.1109/iedm.2012.6478969 ◽

2012 ◽

Author(s):

C.-H. Jan ◽

U. Bhattacharya ◽

R. Brain ◽

S.-J. Choi ◽

G. Curello ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

High Density ◽

Ultra Low Power ◽

High K ◽

Platform Technology

Download Full-text

Advanced Dual Metal Gate MOSFETs with High-k Dielectric for CMOS Application

2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. ◽

10.1109/vlsit.2006.1705192 ◽

2006 ◽

Author(s):

P.F. Hsu ◽

J.M. Chiou ◽

K.M. Yin ◽

J.J Lee ◽

R.L. Hwang ◽

...

Keyword(s):

High K ◽

High K Dielectric

Download Full-text

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

Solid-State Electronics ◽

10.1016/j.sse.2013.02.026 ◽

2013 ◽

Vol 84 ◽

pp. 22-27 ◽

Author(s):

R. Ritzenthaler ◽

T. Schram ◽

E. Bury ◽

A. Spessot ◽

C. Caillat ◽

...

Keyword(s):

Low Power ◽

Gate Stacks ◽

Download Full-text

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

2011 International Electron Devices Meeting ◽

10.1109/iedm.2011.6131556 ◽

2011 ◽

Author(s):

H.-J. Cho ◽

K.-I. Seo ◽

W.C. Jeong ◽

Y.-H. Kim ◽

Y.D. Lim ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Cmos Technology ◽

Technology Platform ◽

Download Full-text