Electrical characterization of gate oxides by scanning probe microscopies

We report on the use of scanning force microscopy as a versatile tool for the electrical characterization of nanoscale memristors fabricated on ultrathin La0.7Sr0.3MnO3 (LSMO) films. Combining conventional conductive imaging and nanoscale lithography, reversible switching between low-resistive (ON) and high-resistive (OFF) states was locally achieved by applying voltages within the range of a few volts. Retention times of several months were tested for both ON and OFF states. Spectroscopy modes were used to investigate the I–V characteristics of the different resistive states. This permitted the correlation of device rectification (reset) with the voltage employed to induce each particular state. Analytical simulations by using a nonlinear dopant drift within a memristor device explain the experimental I–V bipolar cycles.

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Electrical characterization of semiconductor nanowires by scanning-probe microscopy

Semiconductor Nanowires ◽

10.1016/b978-1-78242-253-2.00010-4 ◽

2015 ◽

pp. 277-304 ◽

Cited By ~ 2

Author(s):

T. Xu ◽

B. Grandidier

Keyword(s):

Scanning Probe Microscopy ◽

Electrical Characterization ◽

Semiconductor Nanowires ◽

Scanning Probe ◽

Probe Microscopy

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Electrical characterization of semiconductor materials and devices using scanning probe microscopy

Materials Science in Semiconductor Processing ◽

10.1016/s1369-8001(00)00174-8 ◽

2001 ◽

Vol 4 (1-3) ◽

pp. 71-76 ◽

Cited By ~ 36

Author(s):

P. De Wolf ◽

E. Brazel ◽

A. Erickson

Keyword(s):

Scanning Probe Microscopy ◽

Electrical Characterization ◽

Scanning Probe ◽

Semiconductor Materials ◽

Probe Microscopy

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Evaluation Of 2.0 nm Grown and Deposited Dielectrics in 0.1 μm PMOSFETs

MRS Proceedings ◽

10.1557/proc-525-163 ◽

1998 ◽

Vol 525 ◽

Author(s):

A. Srivastava ◽

H. H. Heinisch ◽

E. Vogel ◽

C. Parker ◽

C. M. Osburn ◽

...

Keyword(s):

Gate Dielectrics ◽

Electrical Characterization ◽

Deposition Process ◽

Gate Oxides ◽

Boron Doped ◽

Excellent Control ◽

Lower Temperature ◽

Boron Penetration

ABSTRACTThe quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.

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Electrical characterization of ultra-thin gate oxides on Si/Si1-x-yGexCy/Si quantum well heterostructures

Semiconductor Science and Technology ◽

10.1088/0268-1242/15/7/317 ◽

2000 ◽

Vol 15 (7) ◽

pp. 761-765 ◽

Cited By ~ 3

Author(s):

S Maikap ◽

S K Ray ◽

S John ◽

S K Banerjee ◽

C K Maiti

Keyword(s):

Quantum Well ◽

Electrical Characterization ◽

Gate Oxides

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Implementation of Sub-Resolvable Features for Precise Electrical Characterization of SiC Gate Oxide Parameters

Materials Science Forum ◽

10.4028/www.scientific.net/msf.717-720.797 ◽

2012 ◽

Vol 717-720 ◽

pp. 797-800

Author(s):

J. Jay McMahon ◽

Liang Chun Yu ◽

Jody Fronheiser ◽

J.T. Elson ◽

Roger Kovalec ◽

...

Keyword(s):

Electrical Characterization ◽

Gate Oxide ◽

Screening Tests ◽

Compensation Mechanism ◽

Gate Oxides ◽

Attractive Option ◽

Van Der Pauw ◽

Similar Yield

We describe fabrication of Van der Pauw (VDP) structures for characterization of gate oxides grown on 4H SiC epi surfaces. Implementation of sub-resolvable features (SRF) as a corner compensation mechanism is analyzed with challenges and advantages presented. Results of on-wafer screening tests suggest that implementation of SRFs widens tolerance for misalignment, producing similar yield between uncompensated VDPs with 0.2 micron overlap and compensated VDPs with 0.1 micron overlap for structures with best alignment. Optimization of SRFs for SiC could be an attractive option for extending lithographic capability in advanced devices.

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