Implementation of Sub-Resolvable Features for Precise Electrical Characterization of SiC Gate Oxide Parameters

We describe fabrication of Van der Pauw (VDP) structures for characterization of gate oxides grown on 4H SiC epi surfaces. Implementation of sub-resolvable features (SRF) as a corner compensation mechanism is analyzed with challenges and advantages presented. Results of on-wafer screening tests suggest that implementation of SRFs widens tolerance for misalignment, producing similar yield between uncompensated VDPs with 0.2 micron overlap and compensated VDPs with 0.1 micron overlap for structures with best alignment. Optimization of SRFs for SiC could be an attractive option for extending lithographic capability in advanced devices.

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Characterization of Nitrided Gate Oxide Formed by RTP for SiC MOSFET Application

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.324.221 ◽

2011 ◽

Vol 324 ◽

pp. 221-224 ◽

Cited By ~ 1

Author(s):

Aurore Constant ◽

Philippe Godignon

Keyword(s):

Gate Oxide ◽

Breakdown Field ◽

Gate Oxides ◽

Furnace Process ◽

Surface Pretreatment ◽

Channel Mobility ◽

Conventional Furnace ◽

The One

Gate oxides for SiC lateral MOSFETs have been formed in N2O by rapid thermal processing (RTP) as an alternative to the conventional furnace process. This innovative oxidation method has not only the advantage to significantly reduce the thermal budget compared to a standard oxidation, but also to produce oxide layers with quality comparable to the one grown in a conventional furnace. Moreover, a significant improvement of the oxide quality and MOSFET performance is observed when performing in-situ a H2 anneal prior to oxidation as surface pretreatment. The channel mobility and the breakdown field of the gate oxide are considerably increased.

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Evaluation Of 2.0 nm Grown and Deposited Dielectrics in 0.1 μm PMOSFETs

MRS Proceedings ◽

10.1557/proc-525-163 ◽

1998 ◽

Vol 525 ◽

Author(s):

A. Srivastava ◽

H. H. Heinisch ◽

E. Vogel ◽

C. Parker ◽

C. M. Osburn ◽

...

Keyword(s):

Gate Dielectrics ◽

Electrical Characterization ◽

Deposition Process ◽

Gate Oxides ◽

Boron Doped ◽

Excellent Control ◽

Lower Temperature ◽

Boron Penetration

ABSTRACTThe quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.

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Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.276.87 ◽

2011 ◽

Vol 276 ◽

pp. 87-93

Author(s):

Y.Y. Gomeniuk ◽

Y.V. Gomeniuk ◽

A. Nazarov ◽

P.K. Hurley ◽

Karim Cherkaoui ◽

...

Keyword(s):

Electrical Characterization ◽

Gate Oxide ◽

Interface State ◽

Channel Length ◽

State Density ◽

Interface State Density ◽

Mos Capacitors ◽

Channel Mobility ◽

Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

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TXRF Characterization of Trace Metal Contamination in Thin Gate Oxides

MRS Proceedings ◽

10.1557/proc-259-173 ◽

1992 ◽

Vol 259 ◽

Author(s):

R. S. Hockett ◽

Diane Hymes

Keyword(s):

Metal Contamination ◽

Gate Oxide ◽

Silicon Substrates ◽

Qualitative Information ◽

Gate Oxides ◽

Quantitative Estimates ◽

Oxide Reliability ◽

First Time ◽

Non Destructive

ABSTRACTMetal contamination on the surface of silicon substrates before gate oxidation is known to affect gate oxide reliability. For the first time this study presents a non-destructive, analytical measurement of transition metals in an 8nm gate oxide grown by a 920 °C-10min-dry oxidation of an intentionally contaminated silicon surface. The TECHNOS TREX 610 TXRF anglescan of the gate oxide provides qualitative information on the location of the metals. The data indicate the Fe is on or in the oxide, the Cu is below the oxide, the Zn is on the oxide, and the Ni may be both in the oxide and below the oxide layer. In addition, quantitative estimates from the TXRF data indicate that all the original Fe and Cu are present, while only portions of Zn and Ni are detected after the oxidation.

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