A 20 nm physical gate length NMOSFET with a 1.2 nm gate oxide fabricated by mixed dry and wet hard mask etching

2002 ◽  
Vol 46 (3) ◽  
pp. 349-352 ◽  
Author(s):  
C. Caillat ◽  
S. Deleonibus ◽  
G. Guegan ◽  
M. Heitzmann ◽  
M.E. Nier ◽  
...  
Keyword(s):  
2000 ◽  
Vol 21 (4) ◽  
pp. 173-175 ◽  
Author(s):  
S. Deleonibus ◽  
C. Caillat ◽  
G. Guegan ◽  
M. Heitzmann ◽  
M.E. Nier ◽  
...  
Keyword(s):  

1998 ◽  
Vol 37 (Part 1, No. 10) ◽  
pp. 5519-5525 ◽  
Author(s):  
Masaaki Sato ◽  
Yoshio Kawai

Author(s):  
Angada B. Sachid ◽  
Roswald Francis ◽  
Maryam Shojaei Baghini ◽  
Dinesh K. Sharma ◽  
Karl-Heinz Bach ◽  
...  
Keyword(s):  

2007 ◽  
Author(s):  
Wen-Shiang Liao ◽  
Tung-Hung Chen ◽  
Hsin-Hung Lin ◽  
Wen-Tung Chang ◽  
Tommy Shih ◽  
...  
Keyword(s):  

Author(s):  
Than Phyo Kyaw

The influence of the GaN buffer layer doped with carbon on the avalanche breakdown effect of normally open HEMT AlGaN / AlN / GaN transistors was studied. The avalanche breakdown was simulated in a structure where the gate length is LG = 0.3 mkm, the distance between the source and gate is LSG = 1.5 mkm, and the distance between the gate and drain is LGD = 2.2 mkm. For modeling, consider a layer doped with carbon, the thickness of which is 0.3 mkm, and the layer is located at a distance of 20 nm from the channel. The Simulation showed that with an increase in the concentration of carbon doping of the buffer, the breakdown voltage increases in the range UB = 225 – 360 (V). When the layer thickness changes to 0.4 mkm, the breakdown voltage increases in the range UB = 230 – 446 (V). For a structure where the gate length is LG = 0.8 mkm, the distance between the source and the gate is LSG = 1.0 mkm, the distance between the gate and drain is LGD = 3.0 mkm, the breakdown voltage increases in the range UB = 300 – 622 (V).


2012 ◽  
Vol 11 (4) ◽  
pp. 808-817 ◽  
Author(s):  
Brahim Benbakhti ◽  
Antonio Martinez ◽  
Karol Kalna ◽  
Geert Hellings ◽  
Geert Eneman ◽  
...  

2021 ◽  
Vol 20 ◽  
pp. 33-38
Author(s):  
Huseyin Ekinci ◽  
Navid M.S. Jahed ◽  
Mohammad Soltani ◽  
Bo Cui

2021 ◽  
Author(s):  
Peng Cui ◽  
Yuping Zeng

Abstract Due to the low cost and the scaling capability of Si substrate, InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions. In this paper, a high-performance 50-nm-gate-length InAlN/GaN HEMT on Si with a high on/off current (Ion/Ioff) ratio of 7.28 × 106, an average subthreshold swing (SS) of 72 mV/dec, a low drain-induced barrier lowing (DIBL) of 88 mV, an off-state three-terminal breakdown voltage (BVds) of 36 V, a current/power gain cutoff frequency (fT/fmax) of 140/215 GHz, and a Johnson’s figure-of-merit (JFOM) of 5.04 THz∙V is simultaneously demonstrated. The device extrinsic and intrinsic parameters are extracted using equivalent circuit model, which is verified by the good agreement between simulated and measured S-parameter values. Then the scaling behavior of InAlN/GaN HEMTs on Si is predicted using the extracted extrinsic and intrinsic parameters of devices with different gate lengths (Lg). It presents that a fT/fmax of 230/327 GHz can be achieved when Lg­ scales down to 20 nm with the technology developed in the study, and an improved fT/fmax of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrown ohmic contact technology and 30% decreased parasitic capacitance. This study confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.


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