In contemporary world the technology has kept its vast identity in developing ultra NANO devices to give up the compact device utilities, in VLSI, Metal Oxide Semiconductor device plays an key role in power dissipation product, in terms of MOS theory characteristics it is predefined that a MOS transistor can conduct easily with low voltage which gives low power but in DSM technology there is a likelihood to achieve ultra low power, so this can be achieved due to the rapid shrinking of gate length, here the chapter deals with challenges and limitations of low power techniques. The predominant way to generate low power is to start with the fundamental principles that are defined in the existing technologies that it gives low power with less leakage current. Apart from this parameter consideration is also required to achieve this. The successful and the major parameter in generating low power is that the shrinking of supply voltage. To go through this, upcoming sections gives the brief idea about the different techniques that are utilized to generate low power with less leakage.
Special Aspects of Submicrometer MOSFETs Simulation for Low Voltage, Ultra-low Power CMOS IC Design