Unified model for QBD prediction for thin gate oxide MOS devices with constant voltage and current stress

2000 ◽  
Vol 51-52 ◽  
pp. 357-372 ◽  
Author(s):  
Mohammed T. Quddus ◽  
Thomas A. DeMassa ◽  
Julian J. Sanchez
Keyword(s):  
Gate Oxide ◽  
Unified Model ◽  
Constant Voltage ◽  
Current Stress ◽  
Mos Devices ◽  
Thin Gate Oxide

Gate Tunneling Current Predicting Model for Scaled NMOSFET Devices

2013 ◽  
Vol 772 ◽  
pp. 422-426
Author(s):  
Zhi Chao Zhao ◽  
Tie Feng Wu ◽  
Hui Bin Ma ◽  
Quan Wang ◽  
Jing Li
Keyword(s):  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Integral Approach ◽  
Predicting Model ◽  
Mos Devices ◽  
Gate Oxide Thickness ◽  
Novel Theory ◽  
Gate Tunneling ◽  
Thin Gate Oxide

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

Single Event Gate Rupture in SiC MOS Capacitors with Different Gate Oxide Thicknesses

2014 ◽  
Vol 778-780 ◽  
pp. 440-443 ◽  
Author(s):  
Manato Deki ◽  
Takahiro Makino ◽  
Kazutoshi Kojima ◽  
Takuro Tomita ◽  
Takeshi Ohshima
Keyword(s):  
Dielectric Breakdown ◽  
Ion Irradiation ◽  
Gate Oxide ◽  
Heavy Ion ◽  
Single Event ◽  
Leakage Currents ◽  
Mos Capacitors ◽  
Heavy Ion Irradiation ◽  
Mos Devices ◽  
Thin Gate Oxide

The leakage currents through the gate oxide of MOS capacitors fabricated on n-type 4H-Silicon Carbide (SiC) was measured under accumulation bias conditions with heavy-ion irradiation. The Linear Energy Transfer (LET) dependence of the critical electric field (Ecr) at which dielectric breakdown occurred in these capacitors with two different oxide thicknesses was evaluated. The MOS capacitors with thin gate oxide showed higherEcrvalues than those with thick gate oxide. The linear relationship between the reciprocalEcrandLETwas observed for both MOS capacitors. The slope ofLETdependence of 1/Ecrfor SiC MOS capacitors was smaller than that for Si, suggesting that SiC MOS devices are less susceptible to single-event gate rupture (SEGR) than Si MOS devices.

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

2005 ◽  
Vol 14 (9) ◽  
pp. 1886-1891 ◽  
Author(s):  
Wang Yan-Gang ◽  
Xu Ming-Zhen ◽  
Tan Chang-Hua ◽  
Zhang J F. ◽  
Duan Xiao-Rong
Keyword(s):  
Leakage Current ◽  
Conduction Mechanism ◽  
Gate Oxide ◽  
Constant Voltage ◽  
Stress Induced Leakage Current ◽  
Thin Gate Oxide

Impact of Post-Trench Processing on the Electrical Characteristics of 4H-SiC Trench-MOS Structures with Thick Top and Bottom Oxides

2015 ◽  
Vol 821-823 ◽  
pp. 753-756 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Martin Rambach ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Inert Gas ◽  
Breakdown Field ◽  
Wafer Surface ◽  
Mos Devices ◽  
Uniform Current ◽  
Thin Gate Oxide ◽  
Mos Structures

This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 °C are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO2) both at the wafer surface (‘top’) and in the bottom of the trenches (‘bottom’) in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 °C and 1550 °C yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO2 gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 °C confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm² have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.

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