Fixed-charge generation in SiO2/GaN MOS structures by forming gas annealing and its suppression by controlling Ga-oxide interlayer growth

A recent study has shown that anomalous positive fixed charge is generated at SiO2/GaN interfaces by forming gas annealing (FGA). Here, we conducted systematic physical and electrical characterizations of GaN-based metal-oxide-semiconductor (MOS) structures to gain insight into the charge generation mechanism and to design optimal interface structures. A distinct correlation between the amount of FGA-induced fixed charge and interface oxide growth indicated the physical origins of the fixed charge to be defect formation driven by reduction of the Ga-oxide (GaOx) interlayer. This finding implies that, although post-deposition annealing in oxygen compensates for oxygen deficiencies and FGA passivates defect in GaN MOS structures, excessive interlayer GaOx growth leads to instability in the subsequent FGA treatment. On the basis of this knowledge, SiO2/GaOx/GaN MOS devices with improved electrical properties were fabricated by precisely controlling the interfacial oxide growth while taking advantage of defect passivation with FGA.

GaN MOS Structures with Low Interface Trap Density

GaN based electronic devices have gained great success in the arena of high-frequency and high-power applications. A high-quality GaN MOS structure has the potential to enable new device designs and higher device performance, thereby bringing the success of GaN electronics to a new level. This paper discusses results of the work on GaN MOS structures show that with adequate surface preparation samples featuring interface trap density down to the ~ 1010 eV-1cm-2 range can be formed.

Tunneling Effects in NH3 Annealed 4H-SiC Trench MOSFETs

The interface between the gate oxide and silicon carbide (SiC) has a strong influence on the performance and reliability of SiC MOSFETs and thus, requires special attention. In order to reduce charge trapping at the interface, post oxidation anneals (POAs) are conventionally applied. However, these anneals do not only influence the device performance, such as mobility and on-resistance, but also the gate oxide reliability. We study the oxide tunneling mechanisms of NH3 annealed 4H-SiC trench MOSFET test structures and compare them to devices which received a NO POA. We show that 3 different mechanisms, namely trap assisted tunneling (TAT), Fowler-Nordheim (FN) tunneling and charge trapping are found for NH3 annealed MOS structures whereas only FN-tunneling is observed in NO annealed devices.The tunneling barrier suggest a trap level with an effective activation energy of 382 meV to enable TAT.