Fully integrated 60 GHz transceiver in SiGe BiCMOS, RF modules, and 3.6 Gbit/s OFDM data transmission

A fully integrated transmitter (TX) and receiver (RX) front-end chipset, produced in 0.25 µm SiGe:C bipolar and complementary metal oxide semiconductor (BiCMOS) technology, is presented. The front-end is intended for high-speed wireless communication in the unlicensed ISM band of 9 GHz around 60 GHz. The TXand RX features a modified heterodyne topology with a sliding intermediate frequency. The TX features a 12 GHz in-phase and quadrature (I/Q) mixer, an intermediate frequency (IF) amplifier, a phase-locked loop, a 60 GHz mixer, an image-rejection filter, and a power amplifier. The RX features a low-noise amplifier (LNA), a 60 GHz mixer, a phase-locked loop (PLL), and an IF demodulator. The measured 1-dB compression point at the TX output is 12.6 dBm and the saturated power is 16.2 dBm. The LNA has measured noise figure of 6.5 dB at 60 GHz. Error-free data transmission with a 16 quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal and data rate of 3.6 Gbit/s (without coding 4.8 Gbit/s) over 15 m was demonstrated. This is the best reported result regarding both the data rate and transmission distance in SiGe and CMOS without beamforming.

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A fully integrated 60 GHz transmitter front-end in SiGe BiCMOS technology

2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems ◽

10.1109/sirf.2011.5719304 ◽

2011 ◽

Cited By ~ 4

Author(s):

S Glisic ◽

K Schmalz ◽

F Herzel ◽

Rouyu Wang ◽

M Elkhouly ◽

...

Keyword(s):

60 Ghz ◽

Fully Integrated ◽

Front End ◽

Bicmos Technology ◽

Sige Bicmos

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A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽

10.3390/electronics10161873 ◽

2021 ◽

Vol 10 (16) ◽

pp. 1873

Author(s):

Chen Cai ◽

Xuqiang Zheng ◽

Yong Chen ◽

Danyu Wu ◽

Jian Luan ◽

...

Keyword(s):

Data Transmission ◽

High Speed ◽

Data Rate ◽

Quality Data ◽

Cmos Process ◽

Voltage Controlled Oscillator ◽

Feed Forward ◽

Fully Integrated ◽

Output Driver ◽

28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

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A 1.5–40 GHz frequency modulated continuous wave radar receiver front-end

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078721000118 ◽

2021 ◽

pp. 1-11

Author(s):

Mantas Sakalas ◽

Niko Joram ◽

Frank Ellinger

Keyword(s):

Continuous Wave ◽

Noise Figure ◽

Supply Voltage ◽

Low Noise ◽

Ultra Wideband ◽

Front End ◽

Wave Radar ◽

Bicmos Technology ◽

Circuit Components ◽

High Band

Abstract This study presents an ultra-wideband receiver front-end, designed for a reconfigurable frequency modulated continuous wave radar in a 130 nm SiGe BiCMOS technology. A variety of innovative circuit components and design techniques were employed to achieve the ultra-wide bandwidth, low noise figure (NF), good linearity, and circuit ruggedness to high input power levels. The designed front-end is capable of achieving 1.5–40 GHz bandwidth, 30 dB conversion gain, a double sideband NF of 6–10.7 dB, input return loss better than 7.5 dB and an input referred 1 dB compression point of −23 dBm. The front-end withstands continuous wave power levels of at least 25 and 20 dBm at low band and high band inputs respectively. At 3 V supply voltage, the DC power consumption amounts to 302 mW when the low band is active and 352 mW for the high band case, whereas the total IC size is $3.08\, {\rm nm{^2}}$ .

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