scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

Fully integrated 60 GHz transceiver in SiGe BiCMOS, RF modules, and 3.6 Gbit/s OFDM data transmission

2011 ◽  
Vol 3 (2) ◽  
pp. 139-145 ◽  
Author(s):  
Srdjan Glisic ◽  
J. Christoph Scheytt ◽  
Yaoming Sun ◽  
Frank Herzel ◽  
Ruoyu Wang ◽  
...  
Keyword(s):  
Data Transmission ◽  
Intermediate Frequency ◽  
Phase Locked Loop ◽  
Data Rate ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Integrated ◽  
Front End ◽  
Free Data ◽  
Bicmos Technology

A fully integrated transmitter (TX) and receiver (RX) front-end chipset, produced in 0.25 µm SiGe:C bipolar and complementary metal oxide semiconductor (BiCMOS) technology, is presented. The front-end is intended for high-speed wireless communication in the unlicensed ISM band of 9 GHz around 60 GHz. The TXand RX features a modified heterodyne topology with a sliding intermediate frequency. The TX features a 12 GHz in-phase and quadrature (I/Q) mixer, an intermediate frequency (IF) amplifier, a phase-locked loop, a 60 GHz mixer, an image-rejection filter, and a power amplifier. The RX features a low-noise amplifier (LNA), a 60 GHz mixer, a phase-locked loop (PLL), and an IF demodulator. The measured 1-dB compression point at the TX output is 12.6 dBm and the saturated power is 16.2 dBm. The LNA has measured noise figure of 6.5 dB at 60 GHz. Error-free data transmission with a 16 quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal and data rate of 3.6 Gbit/s (without coding 4.8 Gbit/s) over 15 m was demonstrated. This is the best reported result regarding both the data rate and transmission distance in SiGe and CMOS without beamforming.

Source Synchronous Double Data Rate (DDR) Parallel Optical Interconnects

2003 ◽  
Author(s):  
Ping Gui ◽  
Fouad Kiamilev ◽  
Xiaoqing Wang ◽  
Michael McFadden ◽  
Charlie Kuznia ◽  
...  
Keyword(s):  
Free Space ◽  
High Speed ◽  
Flip Chip ◽  
Data Rate ◽  
Cavity Surface ◽  
Cmos Process ◽  
Free Space Optical ◽  
Optical Links ◽  
Parallel Optical Interconnects ◽  
Emitting Lasers

Double data rate (DDR) signaling is widely used in electrical interconnects to eliminate clock recovery and to double communication bandwidth. This paper describes the design of a parallel optical transceiver integrated circuit (IC) that uses source-synchronous, DDR optical signaling. On the transmit side, two 8-bit electrical inputs are multiplexed, encoded and sent over two high-speed optical links. On the receive side, the procedure is reversed to produce two 8-bit electrical outputs. Our IC integrates analog Vertical Cavity Surface Emitting Lasers (VCSEL), drivers and optical receivers with digital DDR multiplexing, serialization, and deserializaton circuits. It was fabricated in a 0.5-micron Silicon-on-Sapphire (SOS) CMOS process. Linear arrays of quad VCSELs and photodetectors were attached to our transceiver IC using flip-chip bonding. A free-space optical link system was constructed to demonstrate correct IC functionality. The test results show successful transceiver operation at a data rate of 500 Mbps with a 250 MHz DDR clock, achieving a gigabit of aggregate bandwidth. While our DDR scheme is well suited for low-skew fiber-ribbon, free-space and waveguide optical links, it can also be extended to links with higher skew with the addition of skew-compensation circuitry. To our knowledge, this is the first demonstration of parallel optical transceivers that use source-synchronous DDR signaling.

500 kHz – 5 MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000076-000083 ◽  
Author(s):  
Paul Shepherd ◽  
Ashfaqur Rahman ◽  
Shamim Ahmed ◽  
A Matt Francis ◽  
Jim Holmes ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Extreme Environments ◽  
Phase Locked Loops ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Fully Integrated ◽  
Improved Performance

Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and Voltage Controlled Oscillator components are presented. Operation of the PLL at frequencies up to 1.5 MHz is demonstrated through test results of unpackaged die.

scholarly journals Advanced layout techniques for high‐speed analogue circuits in 28 nm HKMG CMOS process

2018 ◽  
Vol 54 (8) ◽  
pp. 486-488 ◽  
Author(s):  
F. Meng ◽  
K. Li ◽  
D.J. Thomson ◽  
P. Wilson ◽  
G.T. Reed
Keyword(s):  
High Speed ◽  
Cmos Process ◽  
Analogue Circuits ◽  
28 Nm

DESIGN OF A FULLY INTEGRATED 2.4 GHz FREQUENCY PLL SYNTHESIZER FOR ZigBee TRANSCEIVER APPLICATION

2014 ◽  
Vol 23 (10) ◽  
pp. 1450137 ◽  
Author(s):  
DI LI ◽  
YINTANG YANG ◽  
DUAN ZHOU ◽  
YANI LI ◽  
XIAOPENG WU
Keyword(s):  
Frequency Synthesizer ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Frequency Resolution ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Amplitude Control ◽  
Fully Integrated ◽  
Automatic Amplitude Control ◽  
Metal Insulator Metal

A 2.4-GHz fully integrated frequency synthesizer is presented in this paper for Low-IF ZigBee (IEEE802.15.4) transceiver applications. The frequency synthesizer meets the system requirement of 2.4–2.4835 GHz frequency range with a frequency resolution of 5 MHz. The automatic-amplitude control (AAC) technique is employed for the voltage-controlled oscillator (VCO) which helps to optimize the output amplitude of the VCO over voltage, process and temperature variations. The chip has been fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process using a single poly layer, four metal layers and metal–insulator–metal (MIM) capacitors. The synthesized has a current dissipation of 4.7 mA from a 1.8 V power supply and occupies an area of 1 mm2 × 0.85 mm2. Measurement results show that the phase noise are -82 dBc/Hz–100 kHz offset and -109 dBc/Hz–1 MHz offset respectively.

Multi-Thread Chain DMA Data Transfer Method for SuperSpeed Bus Video Transmissions

2014 ◽  
Vol 1046 ◽  
pp. 277-280 ◽  
Author(s):  
Ping Ping Lian
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Video Transmission ◽  
Data Transfer ◽  
Communication Protocol ◽  
High Reliability ◽  
Data Rate ◽  
Video Data ◽  
Usb Bus ◽  
Transfer Method

SuperSpeed bus, also known as USB3.0 bus or SuperSpeed USB bus, is the newest USB bus technology. This paper presents an innovative DMA transfer method called Multi-thread Chain DMA for SuperSpeed bus video data transmissions. The maximum 5Gbps giant data rate of SuperSpeed bus demands a high speed and high reliability DMA method. However, traditional DMA method can not achieve this required data rate due to its separate data transmission and reception. Unlike traditional DMA method, utilizing a novel designed mechanism, Multi-thread Chain DMA transfer method transmits and receives data concurrently, achieves SuperSpeed data rate and guarantees no data loss. Furthermore, one communication protocol for SuperSpeed video transmission is designed and implemented to comply with USB Video Class (UVC) standard. The field trial has demonstrated Multi-thread Chain DMA transfer method and SuperSpeed video communication protocol in the article are feasible and rich in value of research.

scholarly journals A system-on-chip 1.5 GHz phase locked loop realized using 40 nm CMOS technology

2018 ◽  
Vol 31 (1) ◽  
pp. 101-113
Author(s):  
Weiyin Wang ◽  
Xiangjie Chen ◽  
Hei Wong
Keyword(s):  
Cmos Technology ◽  
System On Chip ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Sigma Delta ◽  
Fully Integrated ◽  
Measurement Results ◽  
Feedback Structure ◽  
On Chip ◽  
Frequency Detector

This work presents the design and realization of a fully-integrated 1.5 GHz sigma-delta fractional-N ring-based PLL for system-on-chip (SoC) applications. Some design optimizations were conducted to improve the performance of each functional block such as phase frequency detector (PFD), voltage-controlled oscillator (VCO), filter and charge pump (CP) and so as for the whole system. In particular, a time delay circuit is designed for overcoming the blind zone in the PFD; an operational amplifier-feedback structure was used to eliminate the current mismatch in the CP, a 3rd LPF is used for suppressing noises and a current overdrive structure is used in VCO design. The design was realized with a commercial 40 nm CMOS process. The core die sized about 0.041 mm2. Measurement results indicated that the circuit functions well for the locked range between 500 MHz to 1.5 GHz.

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