scholarly journals High-Performance, Highly Bendable MoS2 Transistors with High-K Dielectrics for Flexible Low-Power Systems

ACS Nano ◽  
2013 ◽  
Vol 7 (6) ◽  
pp. 5446-5452 ◽  
Author(s):  
Hsiao-Yu Chang ◽  
Shixuan Yang ◽  
Jongho Lee ◽  
Li Tao ◽  
Wan-Sik Hwang ◽  
...  
Author(s):  
C. H. Diaz ◽  
K. Goto ◽  
H.T. Huang ◽  
Yuri Yasuda ◽  
C.P. Tsao ◽  
...  
Keyword(s):  

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.


Author(s):  
Minchul Sung ◽  
Se-Aug Jang ◽  
Hyunjin Lee ◽  
Yun-Hyuck Ji ◽  
Jae-Il Kang ◽  
...  
Keyword(s):  

2020 ◽  
Vol 8 (6) ◽  
pp. 4885-4890

This paper presents the novel way to deal with diminish power utilization in a ternary content addressable memory (TCAM) designed in current innovation. The main aim of this TCAM design is to reduce the dynamic power consumption. In TCAM large amount of the power consumption happens during search operation, so we focussed on this area. Here right now give pragmatic plan of a TCAM which is arranged for low-power applications. Simulation of this design has done in Tanned EDA V.16 tool. For simulations of Low power TCAM designs we used predictive technology model (PTM) 45nm for high-performance applications which include metal gate, high-k and stress impact of CMOS technology.


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