scholarly journals Wafer scale synthesis of organic semiconductor nanosheets for van der Waals heterojunction devices

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Sirri Batuhan Kalkan ◽  
Emad Najafidehaghani ◽  
Ziyang Gan ◽  
Fabian Alexander Christian Apfelbeck ◽  
Uwe Hübner ◽  
...  

AbstractOrganic semiconductors (OSC) are widely used for consumer electronic products owing to their attractive properties such as flexibility and low production cost. Atomically thin transition metal dichalcogenides (TMDs) are another class of emerging materials with superior electronic and optical properties. Integrating them into van der Waals (vdW) heterostructures provides an opportunity to harness the advantages of both material systems. However, building such heterojunctions by conventional physical vapor deposition (PVD) of OSCs is challenging, since the growth is disrupted due to limited diffusion of the molecules on the TMD surface. Here we report wafer-scale (3-inch) fabrication of transferable OSC nanosheets with thickness down to 15 nm, which enable the realization of heterojunction devices. By controlled dissolution of a poly(acrylic acid) film, on which the OSC films were grown by PVD, they can be released and transferred onto arbitrary substrates. OSC crystal quality and optical anisotropy are preserved during the transfer process. By transferring OSC nanosheets (p-type) onto prefabricated electrodes and TMD monolayers (n-type), we fabricate and characterize various electronic devices including unipolar, ambipolar and antiambipolar field-effect transistors. Such vdW p-n heterojunction devices open up a wide range of possible applications ranging from ultrafast photodetectors to conformal electronics.

2020 ◽  
Vol 22 (45) ◽  
pp. 26231-26240
Author(s):  
W. X. Zhang ◽  
Y. Yin ◽  
C. He

Graphene-based van der Waals (vdW) heterostructures composed of two-dimensional transition metal dichalcogenides (TMDs) and graphene show great potential in the design and manufacture of field effect transistors.


2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Wei Cao ◽  
Jae Hwan Chu ◽  
Kamyar Parto ◽  
Kaustav Banerjee

AbstractTwo-dimensional (2D) semiconducting materials, in particular transition-metal dichalcogenides, have emerged as the preferred channel materials for sub-5 nm field-effect transistors (FETs). However, the lack of practical doping techniques for these materials poses a significant challenge to designing complementary logic gates containing both n- and p-type FETs. Although electrical tuning of the polarity of 2D-FETs can potentially circumvent this problem, such devices suffer from the lack of balanced n- and p-mode transistor performance, forming one of the most enigmatic challenges of the reconfigurable 2D-FET technology. Here we provide a solution to this dilemma by judicious use of van der Waals (vdW) materials consisting of conductors, dielectrics and semiconductors forming a 50 nm thin quantum engineered strata that can guarantee a purely vdW-type interlayer interaction, which faithfully preserves the mid-gap contact design and thereby achieves an intrinsically mode-balanced and fully reconfigurable all-2D logic gate. The intrinsically mode-balanced gate eliminates the need for transistor sizing and allows post-fabrication reconfigurability to the transistor operation mode, simultaneously allowing an ultra-compact footprint and increased circuit functionality, which can be potentially exploited to build more area-efficient and low-cost integrated electronics for the internet of things (IoT) paradigm.


2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.


2016 ◽  
Vol 8 (24) ◽  
pp. 15574-15581 ◽  
Author(s):  
Yongtao Li ◽  
Yan Wang ◽  
Le Huang ◽  
Xiaoting Wang ◽  
Xingyun Li ◽  
...  

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