In this paper for the first time, the performance of Dielectric Engineered Tunnel Field Effect Transistors (DE-TFETs) is evaluated on the InGaAs channel. Two DE-TFETs based on gate-dielectric structures, namely, Device-A and Device-B are modeled and characterized for both n-type and p-type operations to attain low subthreshold slope (SS) and drain induced barrier lowering (DIBL) using La2O3 as high-k gate dielectric. A structural modification of Device-B is illustrated that improves the on-state current (Ion), SS, and DIBL. Then, performance of both devices are analyzed based on physical oxide thickness (Tox). The simulation results show that the modified Device-B has the lowest SS of 15.31 mV/dec and 54.64 mV/dec, Ion/Ioff ratio of ~109 and ~106 with off-state current (Ioff) of ~10-15 A/µm and ~10-12 A/µm for n-DE-TFET and p-DE-TFET, respectively. Furthermore, the performance parameters of both devices are studied for digital and analog applications and it is found that the modified Device-B can be a potential candidate for future digital applications due to its low power dissipation of 13.55 µW/µm and 27.56 µW/µm for n-DE-TFET and p-DE-TFET, respectively. On the other hand, Device-A shows high transconductance (gm) of 722.52 µS/µm and 424.3 µS/µm and cut-off frequency (fT) of 211.95 GHz and 290.86 GHz for n-DE-TFET and p-DE-TFET, respectively, and can be a viable candidate for future low power analog applications.