Bootstrapped switch without bulk effect in standard CMOS technology

2002 ◽  
Vol 38 (12) ◽  
pp. 555 ◽  
Author(s):  
M. Waltari ◽  
K. Halonen
Keyword(s):  
Cmos Technology ◽  
Bootstrapped Switch ◽  
Bulk Effect

A LOW DISTORTION BOOTSTRAPPED SWITCH FOR 4-BIT MDAC

2013 ◽  
Vol 22 (01) ◽  
pp. 1250074 ◽  
Author(s):  
ZHANGMING ZHU ◽  
GUANGWEN YU ◽  
JINGYU WANG ◽  
YINTANG YANG
Keyword(s):  
Output Voltage ◽  
High Speed ◽  
Dynamic Performance ◽  
Cmos Technology ◽  
Digital Converter ◽  
Analog To Digital ◽  
Low Distortion ◽  
Multiplying Dac ◽  
Bootstrapped Switch ◽  
Switch Circuit

A novel bootstrapped switch scheme with low distortion and high-speed is presented. Transmission gate (TG) switch is used to implement the switch circuit, which results in a reduction in the effect of charge injection during sampling phase and an improved linearity. The parasitic capacitance connected to the top plate of battery capacitor is minimized for higher output voltage. The switch has been simulated in Spectre using an SMIC 0.18 μm CMOS technology at 3.3 V and been applied to a 4-bit multiplying DAC (MDAC) in a 14-bit 100 MS/s pipelined analog-to-digital converter (ADC). The 4-bit MDAC has shown a satisfying dynamic performance.

scholarly journals A 2 GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration in 90 nm CMOS Technology

2017 ◽  
Vol 2017 ◽  
pp. 1-7
Author(s):  
Yi Zhang ◽  
Qiao Meng ◽  
Changchun Zhang ◽  
Ying Zhang ◽  
Yufeng Guo ◽  
...  
Keyword(s):  
Single Channel ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Zero Crossing ◽  
Chip Area ◽  
Analog To Digital ◽  
Bootstrapped Switch ◽  
Foreground Calibration ◽  
Two Stages ◽  
Crossing Point

A single channel 2 GSps, 8-bit folding and interpolation (F&I) analog-to-digital converter (ADC) with foreground calibration in TSMC 90 nm CMOS technology is presented in this paper. The ADC utilizes cascaded folding, which incorporates an interstage sample-and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A master-slave track-and-hold amplifier (THA) with bootstrapped switch is taken as the front-end circuit to improve ADC’s performance. The foreground digital assisted calibration has also been employed to correct the error of zero-crossing point caused by the circuit offset, thus improving the linearity of the ADC. Chip area of the whole ADC including pads is 930 μm × 930 μm. Postsimulation results demonstrate that, under a single supply of 1.2 volts, the power consumption is 210 mW. For the sampling rate of 2 GSps, the signal to noise and distortion ratio (SNDR) is 45.93 dB for Nyquist input signal.

CMOS TECHNOLOGY FOR CCD VIDEO MEMORIES

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-41-C4-44
Author(s):  
G. J.T. DAVIDS ◽  
P. B. HARTOG ◽  
J. W. SLOTBOOM ◽  
G. STREUTKER ◽  
A. G. van der SIJDE ◽  
...  
Keyword(s):  
Cmos Technology

CMOS-TECHNOLOGY - STATUS, TRENDS AND APPLICATIONS

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-13-C4-22
Author(s):  
F. NEPPL ◽  
H.-J. PFLEIDERER
Keyword(s):  
Cmos Technology

CMOS TECHNOLOGY USING PLASMA NITRIDED OXIDE AS A GATE DIELECTRIC

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-421-C4-424 ◽  
Author(s):  
A. STRABONI ◽  
M. BERENGUER ◽  
B. VUILLERMOZ ◽  
P. DEBENEST ◽  
A. VERNA ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Cmos Technology
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