Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications

2004 ◽  
Vol 151 (6) ◽  
pp. 573 ◽  
Author(s):  
M. Yavari ◽  
O. Shoaei
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Switched Capacitor ◽  
Operational Transconductance Amplifiers ◽  
Transconductance Amplifiers ◽  
Fast Settling

Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications

Integration ◽  
2003 ◽  
Vol 36 (4) ◽  
pp. 175-189 ◽  
Author(s):  
Reza Lotfi ◽  
Mohammad Taherzadeh-Sani ◽  
M.Yaser Azizi ◽  
Omid Shoaei
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Low Power Design ◽  
Operational Amplifiers ◽  
Switched Capacitor ◽  
Fast Settling ◽  
Design Techniques

scholarly journals Ultra-Low-Voltage Inverter-Based Operational Transconductance Amplifiers with Voltage Gain Enhancement by Improved Composite Transistors

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1410
Author(s):  
Luis Henrique Rodovalho ◽  
Orazio Aiello ◽  
Cesar Ramos Rodrigues
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Gain ◽  
Design Environment ◽  
Operational Transconductance Amplifiers ◽  
Gain Enhancement ◽  
Transconductance Amplifiers ◽  
Forward Body Bias ◽  
The Cost ◽  
The Impact

This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm2. The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm2. The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.

scholarly journals Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 983 ◽  
Author(s):  
Pedro Toledo ◽  
Paolo Crovetti ◽  
Hamilton Klimach ◽  
Sergio Bampi
Keyword(s):  
Pulse Width Modulation ◽  
Low Voltage ◽  
Process Variations ◽  
Pulse Modulation ◽  
Silicon Area ◽  
Operational Transconductance Amplifiers ◽  
Static Calibration ◽  
Digital Pulse ◽  
Transconductance Amplifiers ◽  
The Impact

The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates by different modulation strategies, i.e., Digital Pulse Width Modulation (DPWM) and Dyadic Digital Pulse Modulation (DDPM), are explored and compared to classic static calibration. The effectiveness of the calibration approaches as a mean to recover acceptable performance in non-functional samples is verified by Monte-Carlo (MC) post-layout simulations performed on a 300 mV power supply, nW-power DB-OTA in 180 nm CMOS. Based on the same MC post-layout simulations, the impact of each calibration strategy on silicon area, power consumption, and OTA performance is discussed.

Sign in / Sign up

Export Citation Format

Share Document