Net-Shape-Based Automated Detection of Integrated-Circuit Layout Plagiarism

Plagiarism of integrated-circuit (IC) layout is a problem encountered both in academia and in industry. A procedure was proposed that compares IC layouts based on the physical representation of particular electrical nets, i.e., on the shape of the features drawn on conducting layers (metals and polysilicon). At the heart of this method is the Needleman–Wunsch algorithm, used for decades in tools aligning sequences of amino acids or nucleotides. Here, it is used to quantify the visual similarity of nets within the pair of layouts being compared. The method was implemented in Python and successfully used to identify clusters of similar layouts within two pools of designs: one composed of logic gates and one containing operational transconductance amplifiers.

CMOS OTA-Based Filters for Designing Fractional-Order Chaotic Oscillators

Fractional-order chaotic oscillators (FOCOs) have shown more complexity than integer-order chaotic ones. However, the majority of electronic implementations were performed using embedded systems; compared to analog implementations, they require huge hardware resources to approximate the solution of the fractional-order derivatives. In this manner, we propose the design of FOCOs using fractional-order integrators based on operational transconductance amplifiers (OTAs). The case study shows the implementation of FOCOs by cascading first-order OTA-based filters designed with complementary metal-oxide-semiconductor (CMOS) technology. The OTAs have programmable transconductance, and the robustness of the fractional-order integrator is verified by performing process, voltage and temperature variations as well as Monte Carlo analyses for a CMOS technology of 180 nm from the United Microelectronics Corporation. Finally, it is highlighted that post-layout simulations are in good agreement with the simulations of the mathematical model of the FOCO.

(N + α)-Order low-pass and high-pass filter transfer functions for non-cascade implementations approximating butterworth response

The formula of the all-pole low-pass frequency filter transfer function of the fractional order (N + α) designated for implementation by non-cascade multiple-feedback analogue structures is presented. The aim is to determine the coefficients of this transfer function and its possible variants depending on the filter order and the distribution of the fractional-order terms in the transfer function. Optimization algorithm is used to approximate the target Butterworth low-pass magnitude response, whereas the approximation errors are evaluated. The interpolated equations for computing the transfer function coefficients are provided. An example of the transformation of the fractional-order low-pass to the high-pass filter is also presented. The results are verified by simulation of multiple-feedback filter with operational transconductance amplifiers and fractional-order element.

Design of Low-Voltage FO-[PD] Controller for Motion Systems

Fractional-order controllers have gained significant research interest in various practical applications due to the additional degrees of freedom offered in their tuning process. The main contribution of this work is the analog implementation, for the first time in the literature, of a fractional-order controller with a transfer function that is not directly constructed from terms of the fractional-order Laplacian operator. This is achieved using Padé approximation, and the resulting integer-order transfer function is implemented using operational transconductance amplifiers as active elements. Post-layout simulation results verify the validity of the introduced procedure.

Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers

Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, different topologies for implementing CMFB are possible, whether using a single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB implementation topology evaluating performance in terms of stability, linearity, noise and common-mode rejection. We present a detailed theoretical analysis, comparing the relative performance of two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our analysis is then corroborated through a case study with full simulation results comparing the two topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used as an example of a high-linearity OTA application, highlighting a 6 dB improvement in P1dB in the multi-loop implementation with respect to the single-loop case.

Self-Biased and Supply-Voltage Scalable Inverter-Based Operational Transconductance Amplifier with Improved Composite Transistors

This paper deals with a single-stage single-ended inverter-based Operational Transconductance Amplifiers (OTA) with improved composite transistors for ultra-low-voltage supplies, while maintaining a small-area, high power-efficiency and low output signal distortion. The improved composite transistor is a combination of the conventional composite transistor and forward-body-biasing to further increase voltage gain. The impact of the proposed technique on performance is demonstrated through post-layout simulations referring to the TSMC 180 nm technology process. The proposed OTA achieves 54 dB differential voltage gain, 210 Hz gain–bandwidth product for a 10 pF capacitive load, with a power consumption of 273 pW with a 0.3 V power supply, and occupies an area of 1026 μm2. For a 0.6 V voltage supply, the proposed OTA improves its voltage gain to 73 dB, and achieves a 15 kHz gain–bandwidth product with a power consumption of 41 nW.

New Resistorless Third-Order Quadrature Sinusoidal Oscillators

This paper introduces four new resistorless, third-order, electronically tunable, quadrature sinusoidal oscillators using three operational transconductance amplifiers (OTAs) and three capacitors. The proposed third-order quadrature sinusoidal oscillators (TOQSOs) provide noninteracting control of the oscillation condition (OC) and oscillation frequency (OF) by changing the transconductance of different OTAs, to produce sustained oscillations and offer quadrature output voltages and currents. Two of the proposed quadrature oscillator circuits have capacitor control of OF, a feature, useful in capacitive transducers. The presented TOQSO structures have good frequency stability and exhibit low active and passive sensitivities. PSPICE simulations using CMOS OTAs along with hardware results (using off-the-shelf available OTA IC LM13700) have also been provided to confirm the workability of the presented circuits.