scholarly journals Ultra-Low-Voltage Inverter-Based Operational Transconductance Amplifiers with Voltage Gain Enhancement by Improved Composite Transistors

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1410
Author(s):  
Luis Henrique Rodovalho ◽  
Orazio Aiello ◽  
Cesar Ramos Rodrigues
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Gain ◽  
Design Environment ◽  
Operational Transconductance Amplifiers ◽  
Gain Enhancement ◽  
Transconductance Amplifiers ◽  
Forward Body Bias ◽  
The Cost ◽  
The Impact

This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm2. The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm2. The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.

scholarly journals Self-Biased and Supply-Voltage Scalable Inverter-Based Operational Transconductance Amplifier with Improved Composite Transistors

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 935
Author(s):  
Luis Henrique Rodovalho ◽  
Cesar Ramos Rodrigues ◽  
Orazio Aiello
Keyword(s):  
Power Consumption ◽  
Power Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Gain ◽  
Gain Bandwidth ◽  
Operational Transconductance Amplifiers ◽  
Transconductance Amplifier ◽  
Technology Process ◽  
The Impact

This paper deals with a single-stage single-ended inverter-based Operational Transconductance Amplifiers (OTA) with improved composite transistors for ultra-low-voltage supplies, while maintaining a small-area, high power-efficiency and low output signal distortion. The improved composite transistor is a combination of the conventional composite transistor and forward-body-biasing to further increase voltage gain. The impact of the proposed technique on performance is demonstrated through post-layout simulations referring to the TSMC 180 nm technology process. The proposed OTA achieves 54 dB differential voltage gain, 210 Hz gain–bandwidth product for a 10 pF capacitive load, with a power consumption of 273 pW with a 0.3 V power supply, and occupies an area of 1026 μm2. For a 0.6 V voltage supply, the proposed OTA improves its voltage gain to 73 dB, and achieves a 15 kHz gain–bandwidth product with a power consumption of 41 nW.

scholarly journals Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 983 ◽  
Author(s):  
Pedro Toledo ◽  
Paolo Crovetti ◽  
Hamilton Klimach ◽  
Sergio Bampi
Keyword(s):  
Pulse Width Modulation ◽  
Low Voltage ◽  
Process Variations ◽  
Pulse Modulation ◽  
Silicon Area ◽  
Operational Transconductance Amplifiers ◽  
Static Calibration ◽  
Digital Pulse ◽  
Transconductance Amplifiers ◽  
The Impact

The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates by different modulation strategies, i.e., Digital Pulse Width Modulation (DPWM) and Dyadic Digital Pulse Modulation (DDPM), are explored and compared to classic static calibration. The effectiveness of the calibration approaches as a mean to recover acceptable performance in non-functional samples is verified by Monte-Carlo (MC) post-layout simulations performed on a 300 mV power supply, nW-power DB-OTA in 180 nm CMOS. Based on the same MC post-layout simulations, the impact of each calibration strategy on silicon area, power consumption, and OTA performance is discussed.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

scholarly journals Low Voltage Electrostatic Actuation and Displacement Measurement Through Resonant Drive Circuit

2012 ◽  
Author(s):  
Sangtak Park ◽  
Eihab Abdel-Rahman
Keyword(s):  
Measurement Method ◽  
Low Voltage ◽  
Supply Voltage ◽  
Numerical Models ◽  
Actuation Voltage ◽  
Input Voltage ◽  
Electrostatic Actuators ◽  
Mems Technology ◽  
Drive Circuit ◽  
The Impact

Most electrostatic actuators fabricated by MEMS technology require high actuation voltage and suffer from the pull-in phenomenon that limits the operation range. We present an amplitude-modulated resonant drive circuit to drive electrostatic actuators at much lower supply voltage than that of conventional actuators to extend their operation range. Analytical and numerical models facilitate stability analysis of electrostatic actuators coupled with the resonant drive circuit. We study the impact of parasitic capacitance and the quality factor of the resonant drive circuit on the operation range of electrostatic actuators. Furthermore, we present a new method to measure the displacement of electrostatic actuators by sensing the phase delay of the actuation voltage with respect to the input voltage. This measurement method allows us to easily incorporate feedback control into existing electrostatic actuators without any modification to the actuator itself.

scholarly journals TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

2019 ◽  
Vol 8 (2S2) ◽  
pp. 226-229
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Large Power ◽  
Flash Adc ◽  
Analog To Digital ◽  
Tiq Comparator ◽  
The Impact

Threshold Inverter Quantization (TIQ) for applications of system-on-chip (SoC) depending on CMOS flash analog-to-digital converter (ADC). The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low-power and low-voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced / managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1]. The findings indicate that the TIQ flash ADC based on Modied mux attain heavy-speed transformation and has a tiny size, low-power dissipation and operation of lowvoltage compared to another flash ADCs.

scholarly journals Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 991
Author(s):  
Joseph Riad ◽  
Sergio Soto-Aguilar ◽  
Johan J. Estrada-López ◽  
Oscar Moreira-Tamayo ◽  
Edgar Sánchez-Sinencio
Keyword(s):  
Cmos Technology ◽  
Common Mode ◽  
Operational Transconductance Amplifiers ◽  
Fully Differential ◽  
Trade Offs ◽  
Active Rc Filter ◽  
Transconductance Amplifiers ◽  
Two Stages ◽  
The Impact

Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, different topologies for implementing CMFB are possible, whether using a single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB implementation topology evaluating performance in terms of stability, linearity, noise and common-mode rejection. We present a detailed theoretical analysis, comparing the relative performance of two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our analysis is then corroborated through a case study with full simulation results comparing the two topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used as an example of a high-linearity OTA application, highlighting a 6 dB improvement in P1dB in the multi-loop implementation with respect to the single-loop case.

Sign in / Sign up

Export Citation Format

Share Document