Ferroelectric-HfO2/oxide interfaces, oxygen distribution effects, and implications for device performance

Chemical Vapor Deposition (CVD) tungsten metallization is used to increase VLSI device performance due to its low resistivity, and improved reliability over other metallization schemes. Because of its conformal nature as a blanket film, CVD-W has been adapted to multiple levels of metal which increases circuit density. It has been used to fabricate 16 MBIT DRAM technology in a manufacturing environment, and is the metallization for 64 MBIT DRAM technology currently under development. In this work, we investigate some sources of contamination. One possible source of contamination is impurities in the feed tungsten hexafluoride (WF6) gas. Another is particle generation from the various reactor components. Another generation source is homogeneous particle generation of particles from the WF6 gas itself. The purpose of this work is to investigate and analyze CVD-W process-generated particles, and establish a particle characterization methodology.

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In situ TEM measurements of the electrical properties of interface dislocations

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100131322 ◽

1992 ◽

Vol 50 (2) ◽

pp. 1338-1339

Author(s):

F. M. Ross ◽

R. Hull ◽

D. Bahnck ◽

J. C. Bean ◽

L. J. Peticolas ◽

...

Keyword(s):

Electrical Properties ◽

Electronic Device ◽

In Situ Tem ◽

Device Performance ◽

Misfit Dislocations ◽

Electrical Characteristics ◽

Strained Layer ◽

Transmission Electron ◽

Interfacial Dislocations

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.

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Charging microscopy and cathodoluminescence imaging of semi-insulating gallium arsenide

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s042482010014542x ◽

1986 ◽

Vol 44 ◽

pp. 816-817

Author(s):

T.C. Sheu ◽

S. Myhajlenko ◽

D. Davito ◽

J.L. Edwards ◽

R. Roedel ◽

...

Keyword(s):

Integrated Circuits ◽

Secondary Electron ◽

Crystal Defects ◽

Device Performance ◽

Gaas Wafer ◽

Surface Charging ◽

Gaas Substrates ◽

Voltage Contrast ◽

Cathodoluminescence Imaging ◽

Scanning Electron

Liquid encapsulated Czochralski (LEC) semi-insulating (SI) GaAs has applications in integrated optics and integrated circuits. Yield and device performance is dependent on the homogeniety of the wafers. Therefore, it is important to characterise the uniformity of the GaAs substrates. In this respect, cathodoluminescence (CL) has been used to detect the presence of crystal defects and growth striations. However, when SI GaAs is examined in a scanning electron microscope (SEM), there will be a tendency for the surface to charge up. The surface charging affects the backscattered and secondary electron (SE) yield. Local variations in the surface charge will give rise to contrast (effectively voltage contrast) in the SE image. This may be associated with non-uniformities in the spatial distribution of resistivity. Wakefield et al have made use of “charging microscopy” to reveal resistivity variations across a SI GaAs wafer. In this work we report on CL imaging, the conditions used to obtain “charged” SE images and some aspects of the contrast behaviour.

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Development of liquid crystal light valves using Bi12SiO20 as the photoconductor. Part 2: Device performance

IEE Proceedings J Optoelectronics ◽

10.1049/ip-j.1986.0009 ◽

1986 ◽

Vol 133 (1) ◽

pp. 65

Author(s):

W.L. Baillie ◽

P.M. Openshaw ◽

A.D. Hart ◽

S.S. Makh

Keyword(s):

Liquid Crystal ◽

Device Performance

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STRUCTURE OF METAL-OXIDE INTERFACES

Le Journal de Physique Colloques ◽

10.1051/jphyscol:1985416 ◽

1985 ◽

Vol 46 (C4) ◽

pp. C4-135-C4-140 ◽

Cited By ~ 2

Author(s):

M. Leseur ◽

B. Pieraggi

Keyword(s):

Metal Oxide ◽

Oxide Interfaces ◽

Structure Of Metal

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METAL-OXIDE INTERFACES OBTAINED BY SELECTIVE CHEMICAL REDUCTION OF LAMELLAR OXIDE-OXIDE EUTECTIC STRUCTURES

Le Journal de Physique Colloques ◽

10.1051/jphyscol:19901122 ◽

1990 ◽

Vol 51 (C1) ◽

pp. C1-781-C1-787

Author(s):

B. BONVALOT ◽

G. DHALENNE ◽

F. MILLOT ◽

A. REVCOLEVSCHI

Keyword(s):

Metal Oxide ◽

Chemical Reduction ◽

Oxide Interfaces ◽

Selective Chemical

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LDPE Building Blocks with Controlled Graphene-oxide Interfaces: Composite Manufacturing and Electric Property Investigation

IEEJ Transactions on Fundamentals and Materials ◽

10.1541/ieejfms.136.93 ◽

2016 ◽

Vol 136 (2) ◽

pp. 93-98 ◽

Cited By ~ 2

Author(s):

Paolo Mancinelli ◽

Valentina Santangelo ◽

Davide Fabiani ◽

Andrea Saccani ◽

Maurizio Toselli ◽

...

Keyword(s):

Graphene Oxide ◽

Building Blocks ◽

Electric Property ◽

Oxide Interfaces ◽

Composite Manufacturing

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Air Bridge Technology: A Comparison of Novel Interconnect Materials and Integration Schemes for Beyond 45 nm

MRS Proceedings ◽

10.1557/proc-766-e5.3 ◽

2003 ◽

Vol 766 ◽

Author(s):

Kenneth Foster ◽

Joost Waeterloos ◽

Don Frye ◽

Steve Froelicher ◽

Mike Mills

Keyword(s):

Dielectric Constants ◽

Advanced Technology ◽

Effective Dielectric Constant ◽

Device Performance ◽

Interlayer Dielectric ◽

Integration Schemes ◽

Stepwise Reduction ◽

Bridge Technology ◽

Integrated Device ◽

Compare And Contrast

AbstractThe electronics industry, in a continual drive for improved integrated device performance, is seeking increasingly lower dielectric constants (k) of the insulators that are used as interlayer dielectric (ILD) for advanced logic interconnects. As the industry continually seeks a stepwise reduction of the “effective” dielectric constant (keff), simple extendibility, leads to the consideration of the highest performance possible, namely air bridge technology. In this paper we will discuss requirements, integration schemes and properties for a novel class of materials that has been developed as part of an advanced technology probe into air bridge architecture. We will compare and contrast these potential technology offerings with other existing dense and porous ILD integration options, and show that the choice is neither trivial nor obvious.

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