Human occupational and performance limits under stress: the thermal environment as a prototypical example

Ergonomics ◽  
1998 ◽  
Vol 41 (8) ◽  
pp. 1169-1191 ◽  
Author(s):  
P. A. HANCOCK ◽  
IOANNIS VASMATZIDIS
1999 ◽  
Vol 85 (2) ◽  
pp. 84-109
Author(s):  
J R House

AbstractA review of the literature on heat strain and aircrew and a questionnaire survey of Royal Navy aircrew have been completed. Aircrew appreciate, some 50% from first hand experience, that heat strain can reduce their operational endurance and performance. They are at greatest risk of developing it in the pre-flight period, especially when wearing Nuclear, Biological, or Chemical (NBC) protective equipment. Several techniques they use to reduce this risk are described. Some may be of particular assistance in the field should air conditioned facilities be unavailable. However, opportunities to improve the thermal environment within the aircraft on the ground and in flight are limited as the heat generated within it and high levels of solar radiation impinging on it severely challenge air conditioning units, themselves constrained by weight and size. Other demands placed on protective clothing offer little potential to increase the rate at which aircrew can lose accumulated heat. It is concluded that an appropriate micro-climate cooling system worn next to the skin may be required to achieve truly significant reductions in heat strain. Research at the Institute of Naval Medicine has identified liquid cooling techniques which may be suitable for aircrew in all but the smallest helicopters.Any views expressed are those of the author and do not necessarily represent those of the Department.


2020 ◽  
Vol 38 (1) ◽  
pp. 180-192 ◽  
Author(s):  
Mahdi Jamei ◽  
Raksha Ramakrishna ◽  
Teklemariam Tesfay ◽  
Reinhard Gentz ◽  
Ciaran Roberts ◽  
...  

The classical planar Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is fabricated by oxidation of a semiconductor namely Silicon. In this generation, an advanced technique called 3D system architecture FETs, are introduced for high performance and low power quality of devices. Based on the limitations of Short Channel Effect (SCE), Silicon (Si) FET cannot be scaled under 10nm. Hence various performing measures like methods, principles, and geometrics are done to upscale the semiconductor. CMOS using alternate channel materials like GE and III-Vs on substrates is a highly anticipated technique for developing nanowire structures. By considering these issues, in this paper, we developed a simulation model that provides accurate results basing on Gate layout and multi-gate NW FET's so that the scaling can be increased few nanometers long and performance limits gradually increases. The model developed is SILVACO that tests the action of FET with different gate oxide materials.


2018 ◽  
Vol 65 (10) ◽  
pp. 4160-4166 ◽  
Author(s):  
Zhipeng Dong ◽  
Huan Zhao ◽  
Don DiMarzio ◽  
Myung-Geun Han ◽  
Lihua Zhang ◽  
...  

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