A COMPACT MODEL FOR THE SIMULATION OF FERROELECTRIC CAPACITOR

2005 ◽  
Vol 75 (1) ◽  
pp. 35-45 ◽  
Author(s):  
JUN YU ◽  
LONGHAI WANG ◽  
YUNBO WANG ◽  
GANG PENG ◽  
FENG LIU ◽  
...  
Keyword(s):  
Compact Model ◽  
Ferroelectric Capacitor

scholarly journals A Computationally Efficient Compact Model for Ferroelectric FinFETs Switching with Asymmetric Non-Periodic Input Signals

2022 ◽  
Author(s):  
Shubham Sahay ◽  
Amol Gaidhane ◽  
Yogesh Singh Chauhan ◽  
Raghvendra Dangi ◽  
Amit Verma
Keyword(s):  
Turning Points ◽  
Compact Model ◽  
Computationally Efficient ◽  
Ferroelectric Capacitor ◽  
Minor Loop ◽  
Dynamic Switching ◽  
Proposed Model ◽  
Input Signals ◽  
Periodic Input ◽  
History Effect

<div>In this paper, we develop a Verilog-A implementable compact model for the dynamic switching of ferroelectric Fin-FETs (Fe-FinFETs) for asymmetric non-periodic input signals. We use the multi-domain Preisach Model to capture the saturated P-E loop of the ferroelectric capacitors. In addition to the saturation loop, we model the history dependent minor loop paths in the P-E by tracing input signals’ turning points. To capture the input signals’ turning points, we propose an R-C circuit based approach in this work. We calibrate our proposed model with the experimental data, and it accurately captures the history effect and minor loop paths of the ferroelectric capacitor. Furthermore, the elimination of storage of each turning point makes the proposed model computationally efficient compared with the previous implementations. We also demonstrate the unique electrical characteristics of Fe-FinFETs by integrating the developed compact model of Fe-Cap with the BSIM-CMG model of 7nm FinFET.</div>

scholarly journals A Computationally Efficient Compact Model for Ferroelectric FinFETs Switching with Asymmetric Non-Periodic Input Signals

2022 ◽  
Author(s):  
Shubham Sahay ◽  
Amol Gaidhane ◽  
Yogesh Singh Chauhan ◽  
Raghvendra Dangi ◽  
Amit Verma
Keyword(s):  
Turning Points ◽  
Compact Model ◽  
Computationally Efficient ◽  
Ferroelectric Capacitor ◽  
Minor Loop ◽  
Dynamic Switching ◽  
Proposed Model ◽  
Input Signals ◽  
Periodic Input ◽  
History Effect

<div>In this paper, we develop a Verilog-A implementable compact model for the dynamic switching of ferroelectric Fin-FETs (Fe-FinFETs) for asymmetric non-periodic input signals. We use the multi-domain Preisach Model to capture the saturated P-E loop of the ferroelectric capacitors. In addition to the saturation loop, we model the history dependent minor loop paths in the P-E by tracing input signals’ turning points. To capture the input signals’ turning points, we propose an R-C circuit based approach in this work. We calibrate our proposed model with the experimental data, and it accurately captures the history effect and minor loop paths of the ferroelectric capacitor. Furthermore, the elimination of storage of each turning point makes the proposed model computationally efficient compared with the previous implementations. We also demonstrate the unique electrical characteristics of Fe-FinFETs by integrating the developed compact model of Fe-Cap with the BSIM-CMG model of 7nm FinFET.</div>

A Compact Model of Polycrystalline Ferroelectric Capacitor

2021 ◽  
pp. 1-4
Author(s):  
Chien-Ting Tung ◽  
Girish Pahwa ◽  
Sayeef Salahuddin ◽  
Chenming Hu
Keyword(s):  
Compact Model ◽  
Ferroelectric Capacitor

Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns

2010 ◽  
Vol E93-C (8) ◽  
pp. 1349-1358
Author(s):  
Kenta YAMADA ◽  
Toshiyuki SYO ◽  
Hisao YOSHIMURA ◽  
Masaru ITO ◽  
Tatsuya KUNIKIYO ◽  
...  
Keyword(s):  
Compact Model

Sky Segmentation for Enhanced Depth Reconstruction and Bokeh Rendering with Efficient Architectures

2020 ◽  
Vol 2020 (14) ◽  
pp. 378-1-378-7
Author(s):  
Tyler Nuanes ◽  
Matt Elsey ◽  
Radek Grzeszczuk ◽  
John Paul Shen
Keyword(s):  
Real Time ◽  
Mobile Device ◽  
Computational Cost ◽  
False Positives ◽  
Compact Model ◽  
High Quality ◽  
False Negatives ◽  
Trade Off ◽  
Depth Reconstruction ◽  
Binary Classifiers

We present a high-quality sky segmentation model for depth refinement and investigate residual architecture performance to inform optimally shrinking the network. We describe a model that runs in near real-time on mobile device, present a new, highquality dataset, and detail a unique weighing to trade off false positives and false negatives in binary classifiers. We show how the optimizations improve bokeh rendering by correcting stereo depth misprediction in sky regions. We detail techniques used to preserve edges, reject false positives, and ensure generalization to the diversity of sky scenes. Finally, we present a compact model and compare performance of four popular residual architectures (ShuffleNet, MobileNetV2, Resnet-101, and Resnet-34-like) at constant computational cost.

ТИРИСТОРНЫЙ ЭФФЕКТ В СВЧ ИС, ИЗГОТОВЛЕННЫХ ПО SIGE БИКМОП-ТЕХНОЛОГИЯМ

2020 ◽  
Vol 96 (3s) ◽  
pp. 612-614
Author(s):  
В.В. Елесина ◽  
И.О. Метелкин
Keyword(s):  
Integrated Circuits ◽  
Extraction Procedure ◽  
Compact Model ◽  
Model Parameters ◽  
Cad Systems ◽  
Parameters Extraction ◽  
Sige Bicmos ◽  
Bicmos Integrated Circuits ◽  
Basic Parameters ◽  
Radiation Induced

Проведен анализ случаев возникновения тиристорного эффекта в СВЧ ИС, изготовленных по технологии SiGe БиКМОП, при воздействии ионизирующего излучения. Рассмотрены области СВЧ ИС, чувствительные к возникновению ТЭ, определены основные параметры тиристорных структур. Проведена апробация подхода к восстановлению параметров схемно-топологической радиационно-ориентированной модели тиристорной структуры для САПР. The paper analyzes ionizing radiation induced latchup in microwave SiGe BiCMOS integrated circuits (ICs). Critical parts of ICs sensitive to latchup have been identified and basic parameters of corresponding parasitic thyristor structures have been determined. An approach has been approved to the thyristor structure compact model parameters extraction procedure intended for use in CAD systems.

Sign in / Sign up

Export Citation Format

Share Document