Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS

2021 ◽  
Vol 16 (12) ◽  
pp. C12010
Author(s):  
L.A. Kadlubowski ◽  
P. Kmon
Keyword(s):  
Single Photon ◽  
Photon Counting ◽  
Cmos Technology ◽  
Time Of Arrival ◽  
Ring Oscillators ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Recording Channel ◽  
Simulation Results ◽  
28 Nm

Abstract The paper describes a design of a prototype chip in 28 nm CMOS technology, consisting of 8 × 4 pixels with 50 μm pitch, dedicated for the precise measurement of Time-of-Arrival (ToA) and Time-over-Threshold (ToT) with a resolution within the picosecond range. To address this requirement, in-pixel Vernier time-to-digital converter (TDC) has been implemented, which utilizes two ring oscillators per pixel. Overall chip architecture is introduced as well as pixel architecture and selected simulation results. The pixel consists of a recording channel and TDC part. The recording channel is composed of an inverter-based front-end amplifier with Zimmerman feedback, a discriminator, a calibration block and a threshold setting block. TDC part includes two ring oscillators together with their calibration blocks and additional logic with counters/shift registers that allow for precise ToA measurement (using Vernier method) as well as ToT measurement (using one of the oscillators). Alternatively, single photon counting (SPC) mode can be used. Frequency of oscillators is set in three steps. First, two global 8-bit digital-to-analog converters (DACs) are used for initial setting of all ring oscillators. Then, per-oscillator capacitance bank and 6-bit DAC are used for fine setting. Simulation results of core blocks suggest that the ToA resolution on the order of tens of picoseconds may be achieved. The chips are already fabricated and are currently being prepared for measurements.

scholarly journals Semidigital PLL Design for Low-Cost Low-Power Clock Generation

2011 ◽  
Vol 2011 ◽  
pp. 1-9
Author(s):  
Ni Xu ◽  
Woogeun Rhee ◽  
Zhihua Wang
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Phase Detection ◽  
Linear Phase ◽  
Digital Converter ◽  
Clock Generation ◽  
Time To Digital Converter ◽  
Simulation Results

This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.

scholarly journals 3D Photon-To-Digital Converter for Radiation Instrumentation: Motivation and Future Works

Sensors ◽  
2021 ◽  
Vol 21 (2) ◽  
pp. 598
Author(s):  
Jean-François Pratte ◽  
Frédéric Nolet ◽  
Samuel Parent ◽  
Frédéric Vachon ◽  
Nicolas Roy ◽  
...  
Keyword(s):  
Large Scale ◽  
Single Photon ◽  
Time Of Flight ◽  
Digital Signal ◽  
Liquid Argon ◽  
Cmos Technology ◽  
System Level ◽  
Superior Performance ◽  
Digital Converter ◽  
Positron Emission

Analog and digital SiPMs have revolutionized the field of radiation instrumentation by replacing both avalanche photodiodes and photomultiplier tubes in many applications. However, multiple applications require greater performance than the current SiPMs are capable of, for example timing resolution for time-of-flight positron emission tomography and time-of-flight computed tomography, and mitigation of the large output capacitance of SiPM array for large-scale time projection chambers for liquid argon and liquid xenon experiments. In this contribution, the case will be made that 3D photon-to-digital converters, also known as 3D digital SiPMs, have a potentially superior performance over analog and 2D digital SiPMs. A review of 3D photon-to-digital converters is presented along with various applications where they can make a difference, such as time-of-flight medical imaging systems and low-background experiments in noble liquids. Finally, a review of the key design choices that must be made to obtain an optimized 3D photon-to-digital converter for radiation instrumentation, more specifically the single-photon avalanche diode array, the CMOS technology, the quenching circuit, the time-to-digital converter, the digital signal processing and the system level integration, are discussed in detail.

scholarly journals A 192×128 Time Correlated Single Photon Counting Imager in 40nm CMOS Technology

2018 ◽  
Author(s):  
Robert K. Henderson ◽  
Nick Johnston ◽  
Haochang Chen ◽  
David Day-Uei Li ◽  
Graham Hungerford ◽  
...  
Keyword(s):  
Single Photon ◽  
Photon Counting ◽  
Cmos Technology ◽  
Single Photon Counting
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