scholarly journals 3D Photon-To-Digital Converter for Radiation Instrumentation: Motivation and Future Works

Sensors ◽  
2021 ◽  
Vol 21 (2) ◽  
pp. 598
Author(s):  
Jean-François Pratte ◽  
Frédéric Nolet ◽  
Samuel Parent ◽  
Frédéric Vachon ◽  
Nicolas Roy ◽  
...  
Keyword(s):  
Large Scale ◽  
Single Photon ◽  
Time Of Flight ◽  
Digital Signal ◽  
Liquid Argon ◽  
Cmos Technology ◽  
System Level ◽  
Superior Performance ◽  
Digital Converter ◽  
Positron Emission

Analog and digital SiPMs have revolutionized the field of radiation instrumentation by replacing both avalanche photodiodes and photomultiplier tubes in many applications. However, multiple applications require greater performance than the current SiPMs are capable of, for example timing resolution for time-of-flight positron emission tomography and time-of-flight computed tomography, and mitigation of the large output capacitance of SiPM array for large-scale time projection chambers for liquid argon and liquid xenon experiments. In this contribution, the case will be made that 3D photon-to-digital converters, also known as 3D digital SiPMs, have a potentially superior performance over analog and 2D digital SiPMs. A review of 3D photon-to-digital converters is presented along with various applications where they can make a difference, such as time-of-flight medical imaging systems and low-background experiments in noble liquids. Finally, a review of the key design choices that must be made to obtain an optimized 3D photon-to-digital converter for radiation instrumentation, more specifically the single-photon avalanche diode array, the CMOS technology, the quenching circuit, the time-to-digital converter, the digital signal processing and the system level integration, are discussed in detail.

Integrating Novel Packaging Technologies for Large Scale Computer Systems

2009 ◽  
Author(s):  
James Mitchell ◽  
John Cunningham ◽  
Ashok V. Krishnamoorthy ◽  
Robert Drost ◽  
Ron Ho
Keyword(s):  
Flash Memory ◽  
Large Scale ◽  
Cmos Technology ◽  
Capacitive Coupling ◽  
System Level ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Large Piece ◽  
Face To Face

Proximity Communication (PxC) enables VLSI chips placed face-to-face to communicate using close-field capacitive coupling. In a 90 nm standard CMOS technology, using the packaging techniques described in this paper, PxC provides chip-to-chip latency of 2.5 ns at 4 Gb/s per channel with less than 2.5 mW/Gb/s, an areal bandwidth density of 0.83 Tb/s/mm2, and a BER less than 10−15. At a system level, the benefits of PxC scale directly with the number of chips that can be packaged together, because PxC enables designers to aggregate multiple chips that perform as a single large piece of silicon. The chips can also be heterogeneous to provide an optimized mix of process technology and functionality, such as integrating DRAM chips, NAND flash memory, and CMOS processor chips. In this paper we describe packaging advances and technology prototypes that enable PxC and provide its system-level benefits.

Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques

2020 ◽  
Vol 17 (4) ◽  
pp. 1595-1599
Author(s):  
N. Suresh ◽  
K. Subba Rao ◽  
R. Vassoudevan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Large Scale ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Essential Components

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

scholarly journals A Multichannel and Compact Time to Digital Converter for Time of Flight Positron Emission Tomography

2015 ◽  
Vol 62 (3) ◽  
pp. 814-823 ◽  
Author(s):  
Nahema Marino ◽  
Federico Baronti ◽  
Luca Fanucci ◽  
Sergio Saponara ◽  
Roberto Roncella ◽  
...  
Keyword(s):  
Positron Emission Tomography ◽  
Time Of Flight ◽  
Emission Tomography ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Positron Emission

scholarly journals DESIGN, IMPLEMENTATION AND ANALYSIS OF FLASH ADC ARCHITECTURE WITH DIFFERENTIAL AMPLIFIER AS COMPARATOR USING CUSTOM DESIGN APPROACH

2012 ◽  
pp. 51-56
Author(s):  
CHANNAKKA LAKKANNAVAR ◽  
SHRIKANTH K. SHIRAKOL ◽  
KALMESHWAR N. HOSUR
Keyword(s):  
Data Storage ◽  
High Speed ◽  
Digital Signal ◽  
Building Blocks ◽  
Input Voltage ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital

Analog-to-Digital Converters (ADCs) are useful building blocks in many applications such as a data storage read channel and an optical receiver because they represent the interface between the real world analog signal and the digital signal processors. Many implementations have been reported in the literature in order to obtain high-speed analog-todigital converters (ADCs). In this paper an effort is made to design 4-bit Flash Analog to Digital Converter [ADC] using 180nm cmos technology. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption are the three key parameters for an Analog-to-Digital Converter (ADC). The integrated flash ADC is operated at 4-bit precision with analog input voltage of 0 to 1.8V. The ADC has been designed, implemented & analysed in standard gpdk180nm technology library using Cadence tool.

Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS

2021 ◽  
Vol 16 (12) ◽  
pp. C12010
Author(s):  
L.A. Kadlubowski ◽  
P. Kmon
Keyword(s):  
Single Photon ◽  
Photon Counting ◽  
Cmos Technology ◽  
Time Of Arrival ◽  
Ring Oscillators ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Recording Channel ◽  
Simulation Results ◽  
28 Nm

Abstract The paper describes a design of a prototype chip in 28 nm CMOS technology, consisting of 8 × 4 pixels with 50 μm pitch, dedicated for the precise measurement of Time-of-Arrival (ToA) and Time-over-Threshold (ToT) with a resolution within the picosecond range. To address this requirement, in-pixel Vernier time-to-digital converter (TDC) has been implemented, which utilizes two ring oscillators per pixel. Overall chip architecture is introduced as well as pixel architecture and selected simulation results. The pixel consists of a recording channel and TDC part. The recording channel is composed of an inverter-based front-end amplifier with Zimmerman feedback, a discriminator, a calibration block and a threshold setting block. TDC part includes two ring oscillators together with their calibration blocks and additional logic with counters/shift registers that allow for precise ToA measurement (using Vernier method) as well as ToT measurement (using one of the oscillators). Alternatively, single photon counting (SPC) mode can be used. Frequency of oscillators is set in three steps. First, two global 8-bit digital-to-analog converters (DACs) are used for initial setting of all ring oscillators. Then, per-oscillator capacitance bank and 6-bit DAC are used for fine setting. Simulation results of core blocks suggest that the ToA resolution on the order of tens of picoseconds may be achieved. The chips are already fabricated and are currently being prepared for measurements.

PET in patients with clear-cut multiple chemical sensitivity (MCS)

2002 ◽  
Vol 41 (06) ◽  
pp. 233-239 ◽  
Author(s):  
C. Hausteiner ◽  
A. Drzezga ◽  
P. Bartenstein ◽  
M. Schwaiger ◽  
H. Förstl ◽  
...  
Keyword(s):  
Single Photon ◽  
Photon Emission ◽  
Multiple Chemical Sensitivity ◽  
Environmental Chemicals ◽  
Chemical Sensitivity ◽  
Clear Cut ◽  
Positron Emission ◽  
Symptom Complex ◽  
Brain Changes ◽  
Multiple Chemical

SummaryAim: Multiple chemical sensitivity (MCS) is a controversially discussed symptom complex. Patients afflicted by MCS react to very low and generally nontoxic concentrations of environmental chemicals. It has been suggested that MCS leads to neurotoxic damage or neuroimmunological alteration in the brain detectable by positron emission tomography (PET) and single photon emission computer tomography (SPECT). These methods are often applied to MCS patients for diagnosis, although they never proved appropriate. Method: We scanned 12 MCS patients with PET, hypothesizing that it would reveal abnormal findings. Results: Mild glucose hypometabolism was present in one patient. In comparison with normal controls, the patient group showed no significant functional brain changes. Conclusion: This first systematic PET study in MCS patients revealed no hint of neurotoxic or neuroimmuno-logical brain changes of functional significance.

Building a Culture of Ethical, Comparable, Authentic Assessment

2019 ◽  
pp. 463-481
Author(s):  
Andrew Reid ◽  
Julie Ballantyne
Keyword(s):  
Teaching And Learning ◽  
Large Scale ◽  
Authentic Assessment ◽  
Subject Area ◽  
Music Educators ◽  
System Level ◽  
Diverse Range ◽  
Effective Learning ◽  
School Based ◽  
The Subject

In an ideal world, assessment should be synonymous with effective learning and reflect the intricacies of the subject area. It should also be aligned with the ideals of education: to provide equitable opportunities for all students to achieve and to allow both appropriate differentiation for varied contexts and students and comparability across various contexts and students. This challenge is made more difficult in circumstances in which the contexts are highly heterogeneous, for example in the state of Queensland, Australia. Assessment in music challenges schooling systems in unique ways because teaching and learning in music are often naturally differentiated and diverse, yet assessment often calls for standardization. While each student and teacher has individual, evolving musical pathways in life, the syllabus and the system require consistency and uniformity. The challenge, then, is to provide diverse, equitable, and quality opportunities for all children to learn and achieve to the best of their abilities. This chapter discusses the designing and implementation of large-scale curriculum as experienced in secondary schools in Queensland, Australia. The experiences detailed explore the possibilities offered through externally moderated school-based assessment. Also discussed is the centrality of system-level clarity of purpose, principles and processes, and the provision of supportive networks and mechanisms to foster autonomy for a diverse range of music educators and contexts. Implications for education systems that desire diversity, equity, and quality are discussed, and the conclusion provokes further conceptualization and action on behalf of students, teachers, and the subject area of music.

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