Low-background neutron reflectometry from solid/liquid interfaces

2022 ◽  
Vol 55 (1) ◽  
Author(s):  
David P. Hoogerheide ◽  
Joseph A. Dura ◽  
Brian B. Maranville ◽  
Charles F. Majkrzak

Liquid cells are an increasingly common sample environment for neutron reflectometry experiments and are critical for measuring the properties of materials at solid/liquid interfaces. Background scattering determines the maximum useful scattering vector, and hence the spatial resolution, of the neutron reflectometry measurement. The primary sources of background are the liquid in the cell reservoir and the materials forming the liquid cell itself. Thus, characterization and mitigation of these background sources are necessary for improvements in the signal-to-background ratio and resolution of neutron reflectometry measurements employing liquid cells. Single-crystal silicon is a common material used for liquid cells due to its low incoherent scattering cross section for neutrons, and the path lengths of the neutron beam through silicon can be several centimetres in modern cell designs. Here, a liquid cell is constructed with a sub-50 µm thick liquid reservoir encased in single-crystal silicon. It is shown that, at high scattering vectors, inelastic scattering from silicon represents a significant portion of the scattering background and is, moreover, structured, confounding efforts to correct for it by established background subtraction techniques. A significant improvement in the measurement quality is achieved using energy-analyzed detection. Energy-analyzed detection reduces the scattering background from silicon by nearly an order of magnitude, and from fluids such as air and liquids by smaller but significant factors. Combining thin liquid reservoirs with energy-analyzed detection and the high flux of the CANDOR polychromatic reflectometer at the NIST Center for Neutron Research, a background-subtracted neutron reflectivity smaller than 10−8 from a liquid cell sample is reported.

Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.


Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 429
Author(s):  
Tengyun Liu ◽  
Peiqi Ge ◽  
Wenbo Bi

Lower warp is required for the single crystal silicon wafers sawn by a fixed diamond wire saw with the thinness of a silicon wafer. The residual stress in the surface layer of the silicon wafer is the primary reason for warp, which is generated by the phase transitions, elastic-plastic deformation, and non-uniform distribution of thermal energy during wire sawing. In this paper, an experiment of multi-wire sawing single crystal silicon is carried out, and the Raman spectra technique is used to detect the phase transitions and residual stress in the surface layer of the silicon wafers. Three different wire speeds are used to study the effect of wire speed on phase transition and residual stress of the silicon wafers. The experimental results indicate that amorphous silicon is generated during resin bonded diamond wire sawing, of which the Raman peaks are at 178.9 cm−1 and 468.5 cm−1. The ratio of the amorphous silicon surface area and the surface area of a single crystal silicon, and the depth of amorphous silicon layer increases with the increasing of wire speed. This indicates that more amorphous silicon is generated. There is both compressive stress and tensile stress on the surface layer of the silicon wafer. The residual tensile stress is between 0 and 200 MPa, and the compressive stress is between 0 and 300 MPa for the experimental results of this paper. Moreover, the residual stress increases with the increase of wire speed, indicating more amorphous silicon generated as well.


Sign in / Sign up

Export Citation Format

Share Document