Smart CMOS focal plane arrays: a Si CMOS detector array and sigma-delta analog-to-digital converter imaging system

As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.

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Optimized System Level Hardware Realization of Built-in-Self-Test Approach for Sigma-Delta Analog-to-Digital Converter

International Journal of Electrical and Electronics Research ◽

10.37391/ijeer.040305 ◽

2016 ◽

Vol 4 (3) ◽

pp. 85-90

Author(s):

Anil Kumar Sahu ◽

Vivek Kumar Chandra ◽

G R Sinha

Keyword(s):

System Level ◽

Dynamic Parameters ◽

Analog To Digital Converter ◽

Digital Converter ◽

Sigma Delta ◽

Matlab Simulink ◽

Analog To Digital ◽

System Level Modeling ◽

Self Test ◽

Sigma Delta Adc

System-level modeling is generally needed due to simultaneous increase in design complexity with multi-million gate designs in today’s system-on-chips (SoCs). System C is generally applied to system-level modeling of Sigma-Delta ADC. CORDIC technique and test generation for the testing of mixed signal circuit components such as analog-to-digital converter is mostly implemented in system level modeling. This work focuses on developing fast and yet accurate model of BIST approach for Sigma-Delta ADC. The Sigma-Delta modulator’s ADC static parameters as well as dynamic parameters are degraded. One of the dynamic parameters, signal-to-noise ratio (SNR) is directly obtained by the SIMSIDES (MATLAB SIMULINK tool). Then, the obtained parameters are tested by using Built-in-self-test that is desirable for the VLSI system in order to reduce the non-recurring cost (NRE) per chip by the manufacturer. This paper demonstrates a possibility to realize a simulation of testing strategy of high-resolution Sigma-Delta modulator using MATLAB SIMULINK and Xilinx EDA tool environment. This work also contributes towards the Output Response Analyzer (ORA) being used for testing parameters which help in reducing the difficulties in design of the complete ORA circuit. Moreover, the reusable features of hardware in the computation of different parameters are also improved in the ORA design.

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Odd/Even Order Sampling Soft-Core Architecture towards Mixed Signals Fourth Industrial Revolution (4IR) Applications

Energies ◽

10.3390/en12234567 ◽

2019 ◽

Vol 12 (23) ◽

pp. 4567

Author(s):

Mfana ◽

Hasan ◽

Ali

Keyword(s):

Industrial Revolution ◽

Dynamic Range ◽

Sampling Frequency ◽

Sampling Techniques ◽

Analog To Digital Converter ◽

Digital Converter ◽

Sigma Delta ◽

Analog To Digital ◽

Fourth Industrial Revolution ◽

Even Order

Digitization is at the center of fourth industrial revolution (4IR) with previously analog systems being digitized through an analog-to-digital converter. In addition, 4IR applications such as fifth generation (5G) Cellular Networks Technology and Cognitive Electronic Warfare (EW) at some point interface digitally through an analog-to-digital converter. Efficient use of digital resources such as memory, largely depends on the signal sampling design of analog-to-digital converters. Existing even order sampling has been found to perform better than traditional sampling techniques. Research on the efficiency of a digital interface with a 4IR platform is still in its infancy. This paper presents a performance study of three sampling techniques: the proposed new and novel odd/even order sampling architecture, existing Mod-∆, and traditional 1st order delta-sigma, to address this. Step-size signal-to-noise (SNR), dynamic range, and sampling frequency are also studied. It was found that the proposed new and novel odd/even order sampling achieved an SNR performance of 6 dB in comparison to 18 dB for Mod-∆. Sampling frequency findings indicated that the proposed new and novel odd/even order sampling achieved a sampling frequency of 2 kHz in comparison to 8 kHz from a traditional 1st order sigma-delta. Dynamic range findings indicated that the proposed odd/even order sampling has achieved a dynamic range of 1.088 volts/ms in comparison to 1.185 volts/ms from a traditional 1st order sigma-delta. Findings have indicated that the proposed odd/even order sampling has superior SNR and sampling frequency performances, while the dynamic range is reduced by 8%.

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