A low-power network for on-line diagnosis of heart patients

IEEE Micro ◽  
1995 ◽  
Vol 15 (3) ◽  
pp. 18-25 ◽  
Author(s):  
R. Coggins ◽  
M. Jabri ◽  
B. Flower ◽  
S. Pickard
Author(s):  
N Poornima ◽  
Seetharaman Gopalakrishnan ◽  
Tughrul Arsalan ◽  
T. N. Prabakar ◽  
M. Santhi

2020 ◽  
Vol 10 (18) ◽  
pp. 6347
Author(s):  
Borja Pozo ◽  
José Ángel Araujo ◽  
Henrik Zessin ◽  
Loreto Mateu ◽  
José Ignacio Garate ◽  
...  

Wind energy harvesting is a widespread mature technology employed to collect energy, but it is also suitable, and not yet fully exploited at small scale, for powering low power electronic systems such as Internet of Things (IoT) systems like structural health monitoring, on-line sensors, predictive maintenance, manufacturing processes and surveillance. The present work introduces a three-phase mini wind energy harvester and an Alternate Current/Direct Current (AC/DC) converter. The research analyzes in depth a wind harvester’s operation principles in order to extract its characteristic parameters. It also proposes an equivalent electromechanical model of the harvester, and its accuracy has been verified with prototype performance results. Moreover, unlike most of the converters which use two steps for AC/DC signal conditioning—a rectifier stage and a DC/DC regulator—this work proposes a single stage converter to increase the system efficiency and, consequently, improve the energy transfer. Moreover, the most suitable AC/DC converter architecture was chosen and optimized for the best performance taking into account: the target power, efficiency, voltage levels, operation frequency, duty cycle and load required to implement the aforementioned converter.


2003 ◽  
Author(s):  
B. Valiquette ◽  
G.L. Torres ◽  
R.P. Malhame ◽  
D. Mukhedkar

2016 ◽  
Vol E99.C (8) ◽  
pp. 909-917
Author(s):  
Akram BEN AHMED ◽  
Hiroki MATSUTANI ◽  
Michihiro KOIBUCHI ◽  
Kimiyoshi USAMI ◽  
Hideharu AMANO

2020 ◽  
Vol 2 (3) ◽  
pp. 158-168
Author(s):  
Muhammad Raza Naqvi

Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.


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