scholarly journals Integration of GalnP/GaAs heterojunction bipolar transistors and high electron mobility transistors

1996 ◽  
Vol 17 (7) ◽  
pp. 363-365 ◽  
Author(s):  
Y.F. Yang ◽  
C.C. Hsu ◽  
E.S. Yang
1991 ◽  
Vol 241 ◽  
Author(s):  
R. A. Metzger ◽  
A. S. Brown ◽  
R. G. Wilson ◽  
T. Liu ◽  
W. E. Stanchina ◽  
...  

ABSTRACTAlInAs and GaInAs lattice matched to InP and grown by MBE over a temperature range of 200 to 350°C (normal growth temperature of 500°C) has been used to enhance the device performance of inverted (where the donor layer lies below the channel) High Electron Mobility Transistors (HEMTs) and Heterojunction Bipolar Transistors (HBTs), respectively. We will show that an AlInAs spacer grown over a temperature range of 300 to 350°C and inserted between the AlInAs donor layer and GaInAs channel significantly reduces Si movement from the donor layer into the channel. This produces an inverted HEMT with a channel charge of 3.0×1012 cm−2 and mobility of 9131 cm2/V-s, as compared to the same HEMT with a spacer grown at 500 °C resulting in a channel charge of 2.3×1012 cm−2 and mobility of 4655 cm2/V-s. We will also show that a GaInAs spacer grown over a temperature range of 300 to 350°C and inserted between the AlInAs emitter and GalnAs base of an npn HBT significantly reduces Be movement from the base into the emitter, thereby allowing higher Be base dopings (up to 1×1020 cm−3) confined to 500 Å base widths, resulting in an AlInAs/GaInAs HBT with an fmax of 73 GHz and ft of 110 GHz.


2021 ◽  
pp. 108050
Author(s):  
Maria Glória Caño de Andrade ◽  
Luis Felipe de Oliveira Bergamim ◽  
Braz Baptista Júnior ◽  
Carlos Roberto Nogueira ◽  
Fábio Alex da Silva ◽  
...  

Author(s):  
Yu-Chen Lai ◽  
Yi-Nan Zhong ◽  
Ming-Yan Tsai ◽  
Yue-Ming Hsin

AbstractThis study investigated the gate capacitance and off-state characteristics of 650-V enhancement-mode p-GaN gate AlGaN/GaN high-electron-mobility transistors after various degrees of gate stress bias. A significant change was observed in the on-state capacitance when the gate stress bias was greater than 6 V. The corresponding threshold voltage exhibited a positive shift at low gate stress and a negative shift when the gate stress was greater than 6 V, which agreed with the shift observation from the I–V measurement. Moreover, the off-state leakage current increased significantly after the gate stress exceeded 6 V during the off-state characterization although the devices could be biased up to 1000 V without breakdown. The increase in the off-state leakage current would lead to higher power loss.


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