Drain-avalanche and hole-trapping induced gate leakage in thin-oxide MOS devices

With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10), Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al2O3/SiO2 interface is also discussed.

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Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Microelectronics Reliability ◽

10.1016/j.microrel.2006.06.002 ◽

2007 ◽

Vol 47 (6) ◽

pp. 937-943 ◽

Cited By ~ 7

Author(s):

W.B. Chen ◽

J.P. Xu ◽

P.T. Lai ◽

Y.P. Li ◽

S.G. Xu

Keyword(s):

Gate Dielectric ◽

Gate Leakage ◽

Mos Devices ◽

High K ◽

High K Gate Dielectric

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Reduced Gate-Leakage Current and Charge Trapping Characteristics of Dysprosium-Incorporated $\hbox{HfO}_{2}$ Gate-Oxide n-MOS Devices

IEEE Transactions on Electron Devices ◽

10.1109/ted.2010.2091453 ◽

2011 ◽

Vol 58 (2) ◽

pp. 562-566 ◽

Cited By ~ 1

Author(s):

Tackhwi Lee ◽

Sanjay K. Banerjee

Keyword(s):

Leakage Current ◽

Charge Trapping ◽

Gate Oxide ◽

Gate Leakage Current ◽

Gate Leakage ◽

Mos Devices

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Interface and Bulk Oxide Damage Induced by Boron Implantation

MRS Proceedings ◽

10.1557/proc-45-53 ◽

1985 ◽

Vol 45 ◽

Author(s):

H. Wong ◽

N.W. Cheung

Keyword(s):

Tunneling Current ◽

Electron Trapping ◽

Constant Voltage ◽

Hole Trapping ◽

Capacitance Voltage ◽

Boron Implantation ◽

Thin Oxide ◽

Oxide Damage

ABSTRACTInvestigations were carried out on the damage of SiO2 and the Si-SiO2 interface induced by boron implantation through polysilicon/SiO2 /p-Si structures with doses up to 1014cm−2 and annealed at 950°C. Using the constant voltage stressing technique, both capacitance-voltage and thin-oxide tunneling current measurements showed that both electron trapping and hole trapping are increased, and that ion-induced electron trapping overcompetes hole trapping for boron doses higher than 5×1013cm−2.

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Differentiating impacts of hole trapping vs. interface states on TDDB reduction in thin oxide gated diode structures

31st Annual Proceedings Reliability Physics 1993 ◽

10.1109/relphy.1993.283315 ◽

1993 ◽

Cited By ~ 3

Author(s):

Y. Tang ◽

C. Chang ◽

S. Haddad ◽

A. Wang ◽

J. Lien

Keyword(s):

Interface States ◽

Hole Trapping ◽

Thin Oxide

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Modeling gate leakage current in nMOS structures due to tunneling through an ultra-thin oxide

Solid-State Electronics ◽

10.1016/s0038-1101(98)00097-5 ◽

1998 ◽

Vol 42 (6) ◽

pp. 997-1006 ◽

Cited By ~ 66

Author(s):

Wei-Kai Shih ◽

Everett X. Wang ◽

Srinivas Jallepalli ◽

Francisco Leon ◽

Christine M. Maziar ◽

...

Keyword(s):

Leakage Current ◽

Gate Leakage Current ◽

Gate Leakage ◽

Thin Oxide

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IVB-2 characterization of tunneling in ultra-thin oxide MOS devices

IEEE Transactions on Electron Devices ◽

10.1109/t-ed.1981.20559 ◽

1981 ◽

Vol 28 (10) ◽

pp. 1237-1237 ◽

Cited By ~ 2

Author(s):

C. Chang ◽

R.W. Brodersen

Keyword(s):

Mos Devices ◽

Thin Oxide

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Impact of NO Annealing on Flatband Voltage Instability due to Charge Trapping in SiС MOS Devices

Materials Science Forum ◽

10.4028/www.scientific.net/msf.858.599 ◽

2016 ◽

Vol 858 ◽

pp. 599-602 ◽

Cited By ~ 14

Author(s):

Yoshihito Katsu ◽

Takuji Hosoi ◽

Yuichiro Nanen ◽

Tsunenobu Kimoto ◽

Takayoshi Shimura ◽

...

Keyword(s):

High Stress ◽

Charge Trapping ◽

Oxide Semiconductor ◽

Mos Capacitor ◽

Hole Trapping ◽

Uv Illumination ◽

Mos Devices ◽

Voltage Stress ◽

Flatband Voltage

We evaluated the effect of NO annealing on hole trapping characteristic of SiC metal-oxide-semiconductor (MOS) capacitor by measuring flatband voltage (VFB) shifts during a constant negative gate voltage stress under UV illumination. Under low stress voltages, the VFB shift due to hole trapping was found to be suppressed by NO annealing. However, the VFB shift of the NO-annealed device increases significantly with stress time under high stress voltage conditions, while the device without NO annealing showed only a slight shift. This result implies that NO annealing enhances generation of hole traps, leading to the degradation of SiC-MOS devices in long-term reliability.

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