scholarly journals Low-Power Binary Neuron Circuit With Adjustable Threshold for Binary Neural Networks Using NAND Flash Memory

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 153334-153340
Author(s):  
Sung-Tae Lee ◽  
Sung Yun Woo ◽  
Jong-Ho Lee
Keyword(s):  
Neural Networks ◽  
Low Power ◽  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Neuron Circuit

A Low Power and Area Scalable High Voltage Switch Technique for Low Operation Voltage in MLC NAND Flash Memory

2010 ◽  
Vol E93-C (2) ◽  
pp. 182-186
Author(s):  
Myounggon KANG ◽  
Ki-Tae PARK ◽  
Youngsun SONG ◽  
Sungsoo LEE ◽  
Yunheub SONG ◽  
...  
Keyword(s):  
Low Power ◽  
High Voltage ◽  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory

A Ferroelectric NAND Flash Memory for Low-power and Highly Reliable Enterprise SSDs and a Ferroelectric 6T-SRAM for 0.5V Low-power CPU and SoC

2010 ◽  
Vol 1250 ◽  
Author(s):  
Kousuke Miyaji ◽  
Teruyoshi Hatanaka ◽  
Shuhei Tanakamaru ◽  
Ryoji Yajima ◽  
Shinji Noda ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Leakage Current ◽  
Flash Memory ◽  
Charge Pump ◽  
Memory Cell ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Process Step ◽  
Ferroelectric Layer

AbstractThis paper overview recent research results about ferroelectric FETs such as a Ferroelectric (Fe-) NAND flash memory for enterprise SSDs and a Ferroelectric 6T-SRAM for 0.5V operation low-power CPU and SoC.In the last five years, as the data through internet increases, the power consumption at the data center doubled. To solve the power crisis SSD is expected to replace HDD. For such an enterprise SSD, the Fe-NAND flash memory is most suitable due to a low power consumption and a high reliability. The Fe-NAND is composed of Metal Ferroelectric Insulator Semiconductor transistors. The program/erase voltage decreases from 20V to 6V. In the Fe-NAND, the electric polarization in the ferroelectric layer flips with a lower electric field and the Vth of a memory cell shifts. Due to a low program/erase voltage, a low power operation is achieved. In the Fe-NAND, a high write/erase endurance, 100Million cycle, four orders of magnitudes higher than the conventional NAND, is realized because there is no stress-induced leakage current.The Fe-NAND flash memory with a non-volatile (NV) page buffer is also proposed. The data fragmentation of SSD in a random write is removed by introducing a batch write algorithm. As a result, the SSD performance can double. The NV-page buffer realizes a power outage immune highly reliable operation. In addition, a zero Vth memory cell scheme is proposed to best optimize the reliability of the Fe-NAND. The Vth shift caused by the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively. A 1.2V operation adaptive charge pump circuit for the low voltage and low power Fe-NAND is introduced. By using Fe-FETs as diodes in the charge pump and optimizing the Vth of Fe-FETs at each pump stage, the power efficiency and the output voltage increase by 143% and 25% without the circuit area and process step penalty.Finally, a ferroelectric 6T-SRAM is proposed for the 0.5V operation low power CPU and SoC. During the read/hold, the Vth of Fe-FETs automatically changes to increase the static noise margin by 60%. During the stand-by, the Vth increases to decrease the leakage current by 42%. As a result, the supply voltage by 0.11V, which decreases the active power by 32%.

scholarly journals Operation Scheme of Multi-Layer Neural Networks Using NAND Flash Memory as High-Density Synaptic Devices

2019 ◽  
Vol 7 ◽  
pp. 1085-1093 ◽  
Author(s):  
Sung-Tae Lee ◽  
Suhwan Lim ◽  
Nag Yong Choi ◽  
Jong-Ho Bae ◽  
Dongseok Kwon ◽  
...  
Keyword(s):  
Neural Networks ◽  
Flash Memory ◽  
High Density ◽  
Nand Flash ◽  
Nand Flash Memory

Effect of Word-Line Bias on Linearity of Multi-Level Conductance Steps for Multi-Layer Neural Networks Based on NAND Flash Cells

2020 ◽  
Vol 20 (7) ◽  
pp. 4138-4142
Author(s):  
Sung-Tae Lee ◽  
Suhwan Lim ◽  
Nagyong Choi ◽  
Jong-Ho Bae ◽  
Dongseok Kwon ◽  
...  
Keyword(s):  
Neural Networks ◽  
Flash Memory ◽  
Storage Capacity ◽  
High Density ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Data Set ◽  
Source Line ◽  
In Series ◽  
Multi Level

NAND flash memory which is mature technology has great advantage in high density and great storage capacity per chip because cells are connected in series between a bit-line and a source-line. Therefore, NAND flash cell can be used as a synaptic device which is very useful for a high-density synaptic array. In this paper, the effect of the word-line bias on the linearity of multi-level conductance steps of the NAND flash cell is investigated. A 3-layer perceptron network (784×200×10) is trained by a suitable weight update method for NAND flash memory using MNIST data set. The linearity of multi-level conductance steps is improved as the word line bias increases from Vth −0.5 to Vth +1 at a fixed bit-line bias of 0.2 V. As a result, the learning accuracy is improved as the word-line bias increases from Vth −0.5 to Vth+1.

A Low Power and Improving Read Disturb Characteristics by Using Multi-CSL Architecture in MLC NAND Flash Memory

2010 ◽  
Author(s):  
M. Kang ◽  
K. T. Park ◽  
Y. Song ◽  
S. Lee ◽  
Y. Lim ◽  
...  
Keyword(s):  
Low Power ◽  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory

scholarly journals Modeling of GIDL–Assisted Erase in 3–D NAND Flash Memory Arrays and Its Employment in NOR Flash–Based Spiking Neural Networks

2022 ◽  
pp. 43-53
Author(s):  
Gerardo Malavena
Keyword(s):  
Neural Networks ◽  
Flash Memory ◽  
Computational Effort ◽  
Spiking Neural Networks ◽  
Compact Model ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Arrays ◽  
Tcad Simulations ◽  
Nor Flash

AbstractSince the very first introduction of three-dimensional (3–D) vertical-channel (VC) NAND Flash memory arrays, gate-induced drain leakage (GIDL) current has been suggested as a solution to increase the string channel potential to trigger the erase operation. Thanks to that erase scheme, the memory array can be built directly on the top of a $$n^+$$ n + plate, without requiring any p-doped region to contact the string channel and therefore allowing to simplify the manufacturing process and increase the array integration density. For those reasons, the understanding of the physical phenomena occurring in the string when GIDL is triggered is important for the proper design of the cell structure and of the voltage waveforms adopted during erase. Even though a detailed comprehension of the GIDL phenomenology can be achieved by means of technology computer-aided design (TCAD) simulations, they are usually time and resource consuming, especially when realistic string structures with many word-lines (WLs) are considered. In this chapter, an analysis of the GIDL-assisted erase in 3–D VC nand memory arrays is presented. First, the evolution of the string potential and GIDL current during erase is investigated by means of TCAD simulations; then, a compact model able to reproduce both the string dynamics and the threshold voltage transients with reduced computational effort is presented. The developed compact model is proven to be a valuable tool for the optimization of the array performance during erase assisted by GIDL. Then, the idea of taking advantage of GIDL for the erase operation is exported to the context of spiking neural networks (SNNs) based on NOR Flash memory arrays, which require operational schemes that allow single-cell selectivity during both cell program and cell erase. To overcome the block erase typical of nor Flash memory arrays based on Fowler-Nordheim tunneling, a new erase scheme that triggers GIDL in the NOR Flash cell and exploits hot-hole injection (HHI) at its drain side to accomplish the erase operation is presented. Using that scheme, spike-timing dependent plasticity (STDP) is implemented in a mainstream NOR Flash array and array learning is successfully demonstrated in a prototype SNN. The achieved results represent an important step for the development of large-scale neuromorphic systems based on mature and reliable memory technologies.

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