scholarly journals An 0.4–2.8 GHz CMOS Power Amplifier With On-Chip Broadband-Pre-Distorter (BPD) Achieving 36.1–38.6% PAE and 21 dBm Maximum Linear Output Power

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 48831-48840
Author(s):  
Selvakumar Mariappan ◽  
Jagadheswaran Rajendran ◽  
Yusman M. Yusof ◽  
Norlaili M. Noh ◽  
Binboga Siddik Yarman
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
On Chip

scholarly journals A Fully Integrated Compact Outphasing CMOS Power Amplifier Using a Parallel-Combining Transformer with a Tuning Inductor Method

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 257 ◽  
Author(s):  
Se-Eun Choi ◽  
Hyunjin Ahn ◽  
Joonhoi Hur ◽  
Kwan-Woo Kim ◽  
Ilku Nam ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Cmos Process ◽  
Power Combining ◽  
Fully Integrated ◽  
Term Evolution ◽  
Class D ◽  
Adjacent Channel ◽  
On Chip

This work presents a compact on-chip outphasing power amplifier with a parallel-combining transformer (PCT). A series-combining transformer (SCT) and PCT are analyzed as power-combining transformers for outphasing operations. Compared to the SCT, which is typically used for on-chip outphasing combiners, the PCT is much smaller. The outphasing operations of the transformer combiners and class-D switching PAs are also analyzed. A tuning inductor method is proposed to improve the efficiency of class-D power amplifiers (PAs) with power-combining transformers in the out-of-phase mode. The proposed PA was implemented with a standard 0.18 µm CMOS process. The measured maximum drain efficiency is 37.3% with an output power of 22.4 dBm at 1.7 GHz. A measured adjacent channel leakage ratio (ACLR) of less than −30 dBc is obtained for a long-term evolution (LTE) signal with a bandwidth of 10 MHz.

scholarly journals Efficiency Analysis of Low Power Class-E Power Amplifier

2014 ◽  
Vol 8 (5) ◽  
pp. 19
Author(s):  
Mousa Yousefi ◽  
Ziaadin Daie Koozehkanani ◽  
Jafar Sobhi ◽  
Hamid Jangi ◽  
Nasser Nasirezadeh
Keyword(s):  
Low Power ◽  
Output Power ◽  
Power Amplifier ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Efficiency Analysis ◽  
Simulation Results ◽  
On Chip ◽  
Power Class ◽  
Class E

This paper presents an analysis of effect of inductor and switch losses on output power and efficiency of low power class-E power amplifier. This structure is suitable for integrated circuit implementation. Since on chip inductors have large losses than the other elements, the effect of their losses on efficiency has been investigated. Equations for the efficiency have been derived and plotted versus the value of inductors and switch losses. Derived equations are evaluated using MATLAB. Also, Cadence Spectre has been used for schematic simulation. Results show a fair matching between simulated power loss and efficiency and MATLAB evaluations. Considering the analysis, the proposed power amplifier shows about 13 % improvement in power effiency at 400 MHz and -2 dBm output power. It is simulated in 0.18 ?m CMOS technology.

Failure Localization in a Multistage S-Band Power Amplifier

2016 ◽  
Author(s):  
Clarence Rebello ◽  
Ted Kolasa ◽  
Parag Modi
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Fault Tree ◽  
Root Cause ◽  
Failure Investigation ◽  
Band Power ◽  
Cause Of Failure ◽  
Design Materials ◽  
Board Level ◽  
Failure Localization

Abstract During the search for the root cause of a board level failure, all aspects of the product must be revisited and investigated. These aspects encompass design, materials, and workmanship. In this discussion, the failure investigation involved an S-Band Power Amplifier assembly exhibiting abnormally low RF output power where initial troubleshooting did not provide a clear cause of failure. A detailed fault tree drove investigations that narrowed the focus to a few possible root causes. However, as the investigation progressed, multiple contributors were eventually discovered, some that were not initially considered.

РАЗРАБОТКА СВЧ МОНОЛИТНЫХ ИНТЕГРАЛЬНЫХ СХЕМ МИЛЛИМЕТРОВОГО ДИАПАЗОНА НА ОСНОВЕ GAAS ДЛЯ ПРИМЕНЕНИЯ В СОВРЕМЕННЫХ ИНФОРМАЦИОННОКОММУНИКАЦИОННЫХ СИСТЕМАХ НОВОГО ПОКОЛЕНИЯ (5G)

2020 ◽  
Vol 96 (3s) ◽  
pp. 321-324
Author(s):  
Е.В. Ерофеев ◽  
Д.А. Шишкин ◽  
В.В. Курикалов ◽  
А.В. Когай ◽  
И.В. Федин
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Integrated Circuit ◽  
Phase Shifter ◽  
Phase Error ◽  
Microwave Integrated Circuit ◽  
Gain Compression ◽  
Monolithic Microwave Integrated Circuit ◽  
And Performance ◽  
Power Capability

В данной работе представлены результаты разработки СВЧ монолитной интегральной схемы шестиразрядного фазовращателя и усилителя мощности диапазона частот 26-30 ГГц. СКО ошибки по фазе и амплитуде фазовращателя составили 1,2 град. и 0,13 дБ соответственно. Максимальная выходная мощность и КПД по добавленной мощности усилителя в точке сжатия Ку на 1 дБ составили 30 дБм и 20 % соответственно. This paper describes the design, layout, and performance of 6-bit phase shifter and power amplifier monolithic microwave integrated circuit (MMIC), 26-30 GHz band. Phase shifter MMIC has RMS phase error of 1.2 deg. And RMD amplitude error is 0.13 dB. MMIC power amplifier has output power capability of 30 dBm at 1 dB gain compression (P-1dB) and PAE of 20 %.

A compact H-band Power Amplifier with High Output Power

2021 ◽  
Author(s):  
Ahmed S. H. Ahmed ◽  
Utku Soylu ◽  
Munkyo Seo ◽  
Miguel Urteaga ◽  
Mark J. W. Rodwell
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Output Power ◽  
Band Power ◽  
High Output

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

Sign in / Sign up

Export Citation Format

Share Document