Gain Compression of n-MESFET for High Power Applications in MIMO

In this paper, a new n-type recessed Metal semiconductor field effect transistor (MESFET) with GaAs/ SiC materials is designed for high power applications in Multi Input Multi Output (MIMO) systems. Based on electrical characteristics of MESFET, a SPICE model of the proposed device is developed. For power switches, the power MESFETs are used. The feasibility of the technology is validated by the electrical measurements of the device. The operational technology has been shown by the characterizations done on the proposed device. To optimize the electrical performance, the contact resistance technique has to be enhanced. In this work, the output power and Gain compression of proposed n-channel MESFET at 100 MHz and 1 GHz for high input power is obtained. The output power at fundamental frequency of operation for high input power is also obtained.

4–20mA optical sensor at 300C using SiC and SOI integrated circuits

GE is reporting test results from a hybrid circuit using high temperature capable resistors, capacitors, silicon carbide devices and silicon-on-insulator integrated circuits. The sensing circuit converts photodiode current to an industrial standard 4 to 20 mA output using a two wire configuration. Input currents at levels from 0pA to 30nA is converted to 4 to 20 mA using a gain compression technique and tested from room temperature to 300°C. Further, we show the circuit operating at 300°C for more than 2000 hours without failure.

An Optimal Digital Filtering Technique for Incremental Delta-Sigma ADCs Using Passive Integrators

This paper presents an optimal digital filtering technique to enhance the resolution of incremental delta-sigma modulators (incremental DSMs, IDSMs) using a low-power passive integrator. We first describe a link between a passive integrator and its impact on the output of the IDSM. We then show that the optimal digital filter design can be cast as a convex optimization problem, which can be efficiently solved. As a test vehicle of the proposed technique, we use a behavioral 2nd-order IDSM model that captures critical non-idealities of the integrator, such as gain compression and output saturation. The effectiveness of the presented technique is verified using extensive simulations. The result shows that the presented filtering technique improves signal-to-noise and distortion ratio (SNDR) by 15 dB–20 dB, achieving SNDR over 90 dB when the oversampling ratio (OSR) = 256, and this corresponds to best-in-class performance when compared to previously published DSM designs using passive integrators.

Increased Efficiency of a Current Compensating Load Modulation Based MMIC Doherty Power Amplifier Design In 0.25m GaAs pHEMT Technology

In this work, a premise is applied to the conventional load modulation equation of Doherty power amplifier (DPA) in 0.25 m GaAs pHEMT technology to compensate output impedance of main amplifier ( Z out,main ) variation, even in low power region. Using this modified modulation leads to the DPAs power added efficiency (PAE) increase in comparison by the case in which the load modulation revision is ignored, which is also designed in this paper. Second harmonic rejection networks are also added to both designs to play their roles as to efficiency increase. By doing so, the revised load modulation based DPA has the maximum PAE of 39.6%, maximum output power ( P out ) of 31.61dBm, at 8 GHz. Simulation results of this DPA in higher harmonics indicate the designed DPA has the minimum second and third harmonics power of -51.7 dBm and -80 dBm, respectively. For the sake of linearity evaluation, it is depicted that 1dB-power gain compression has not occurred in the input power (P in ) range in which the proposed DPA works.

РАЗРАБОТКА СВЧ МОНОЛИТНЫХ ИНТЕГРАЛЬНЫХ СХЕМ МИЛЛИМЕТРОВОГО ДИАПАЗОНА НА ОСНОВЕ GAAS ДЛЯ ПРИМЕНЕНИЯ В СОВРЕМЕННЫХ ИНФОРМАЦИОННОКОММУНИКАЦИОННЫХ СИСТЕМАХ НОВОГО ПОКОЛЕНИЯ (5G)

В данной работе представлены результаты разработки СВЧ монолитной интегральной схемы шестиразрядного фазовращателя и усилителя мощности диапазона частот 26-30 ГГц. СКО ошибки по фазе и амплитуде фазовращателя составили 1,2 град. и 0,13 дБ соответственно. Максимальная выходная мощность и КПД по добавленной мощности усилителя в точке сжатия Ку на 1 дБ составили 30 дБм и 20 % соответственно. This paper describes the design, layout, and performance of 6-bit phase shifter and power amplifier monolithic microwave integrated circuit (MMIC), 26-30 GHz band. Phase shifter MMIC has RMS phase error of 1.2 deg. And RMD amplitude error is 0.13 dB. MMIC power amplifier has output power capability of 30 dBm at 1 dB gain compression (P-1dB) and PAE of 20 %.

A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology

We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push–pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Ω load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm2 without pads.