scholarly journals A Fully Integrated Compact Outphasing CMOS Power Amplifier Using a Parallel-Combining Transformer with a Tuning Inductor Method

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 257 ◽  
Author(s):  
Se-Eun Choi ◽  
Hyunjin Ahn ◽  
Joonhoi Hur ◽  
Kwan-Woo Kim ◽  
Ilku Nam ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Cmos Process ◽  
Power Combining ◽  
Fully Integrated ◽  
Term Evolution ◽  
Class D ◽  
Adjacent Channel ◽  
On Chip

This work presents a compact on-chip outphasing power amplifier with a parallel-combining transformer (PCT). A series-combining transformer (SCT) and PCT are analyzed as power-combining transformers for outphasing operations. Compared to the SCT, which is typically used for on-chip outphasing combiners, the PCT is much smaller. The outphasing operations of the transformer combiners and class-D switching PAs are also analyzed. A tuning inductor method is proposed to improve the efficiency of class-D power amplifiers (PAs) with power-combining transformers in the out-of-phase mode. The proposed PA was implemented with a standard 0.18 µm CMOS process. The measured maximum drain efficiency is 37.3% with an output power of 22.4 dBm at 1.7 GHz. A measured adjacent channel leakage ratio (ACLR) of less than −30 dBc is obtained for a long-term evolution (LTE) signal with a bandwidth of 10 MHz.

Design of Unsymmetrical Doherty Power Amplifier for 460MHz LTE-Advanced Applications

2013 ◽  
Vol 347-350 ◽  
pp. 1768-1772
Author(s):  
Chuan Hui Ma ◽  
Wen Sheng Pan ◽  
You Xi Tang ◽  
Chao Jin Qing
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Continuous Wave ◽  
Average Output ◽  
Term Evolution ◽  
Lte Advanced ◽  
Adjacent Channel ◽  
Before And After ◽  
Doherty Power Amplifier

An unsymmetrical Doherty power amplifier (DPA) at 460MHz is presented in this paper. The carrier and peaking amplifier of the DPA, which base on two equal-sized devices, are matched with different networks to mitigate the performance degradation caused by the limited load modulation. Measured with continuous wave (CW), the unsymmetrical DPA saturates at an output power of 49.2dBm and achieves a drain efficiency of 51% at 6dB back-off. Using a one-carrier long term evolution advanced (LTE-Advanced) signal with 20MHz bandwidth, the unsymmetrical DPA exhibits a drain efficiency of 48.7% at an average output power of 42.1dBm, along with adjacent channel leakage ratio (ACLR) of-34.1dBc and-53.3dBc before and after digital pre-distortion (DPD), respectively.

DESIGN OF WIDEBAND LTE POWER AMPLIFIER WITH NOVEL DUAL STAGE LINEARIZER FOR MOBILE WIRELESS COMMUNICATION

2014 ◽  
Vol 23 (08) ◽  
pp. 1450111 ◽  
Author(s):  
U. ESWARAN ◽  
H. RAMIAH ◽  
J. KANESAN ◽  
A. W. REZA
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Path Loss ◽  
Stringent Requirement ◽  
Fully Integrated ◽  
Power Added Efficiency ◽  
Channel Bandwidth ◽  
Dual Stage

In this paper, a 1 mm × 1 mm fully integrated wideband dual-stage power amplifier (PA) for long-term evolution (LTE) band 1 (1920–1980 MHz) is presented. Fabricated in a 2 μm InGaP/GaAs hetero-junction bipolar transistor (HBT) process, the operating gain is observed to be 31.3 dB. The PA meets the minimum adjacent channel leakage ratio (ACLR) requirement of -30 dBc for LTE with 20 MHz wide channel bandwidth up to an output power of 30 dBm with the aid of a novel dual stage linearizer. Biased at low quiescent current of less than 100 mA with a headroom consumption of 3.5 V, the power added efficiency (PAE) is observed to be 38.29% at 30 dBm. With this high linear output power, the stringent requirement of antenna path loss is nullified. PA serves to be the first reported work to achieve 30 dBm linear output power at supply voltage of 3.5 V.

scholarly journals A Fully Integrated Clocked AC-DC Charge Pump for Mignetostrictive Vibration Energy Harvesting

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2194
Author(s):  
Hayato Kawauchi ◽  
Toru Tanzawa
Keyword(s):  
Output Power ◽  
Charge Pump ◽  
Input Voltage ◽  
Open Circuit ◽  
Vibration Energy ◽  
Cmos Process ◽  
Vibration Energy Harvesting ◽  
Fully Integrated ◽  
Energy Transducer ◽  
On Chip

This paper describes a clocked AC-DC charge pump to enable full integration of power converters into a sensor or radio frequency (RF) chip even with low open circuit voltage magnetostrictive vibration energy transducer operating at a low resonant frequency of 10 Hz to 1 kHz. The frequency of the clock to drive an AC-DC charge pump was up-converted with an on-chip oscillator to increase output power of the charge pump without significantly increasing the circuit area. A model of the system including the charge pump and vibration energy transducer is shown. It was validated by HSPICE simulation and measured, resulting in a prototype chip with an area of 0.11 mm2 fabricated in a 65 nm 1 V CMOS process. The fabricated charge pump was also measured together with a magnetostrictive transducer. The charge pump converted the power from the transducer to an output power of 4.2 μW at an output voltage of 2.0 V. The output power varied below 3% over a wide input frequency of 10 Hz to 100 kHz, which suggests that universal design of the clocked AC-DC charge pump can be used for transducers with different resonant frequencies. In a low-input voltage region below 0.8 V, the proposed circuit has higher output power compared with the conventional circuits.

scholarly journals Dual-band doherty power amplifier with improved reactance compensation

2021 ◽  
Vol 23 (3) ◽  
pp. 1550
Author(s):  
Li M. Yu ◽  
Narendra K. Aridas ◽  
Tarik A. Latef
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Electron Mobility ◽  
High Electron Mobility Transistor ◽  
Dual Band ◽  
High Electron ◽  
High Electron Mobility ◽  
Term Evolution ◽  
Doherty Power Amplifier

In brief, a dual-band doherty power amplifier employing reactance compensation with gallium nitride high-electron-mobility transistor technology is discussed. This design is developed for long-term evolution (LTE) frequency operation, particularly for the application of two-way radio to improve the efficiency at the back-off point from saturation output power for selected dual frequencies in the LTE bandwidth. Measurements show that the prototype board has enhanced performance at the desired frequencies, namely a saturation output power of 40.5 dBm, and 6 dB back-off efficiencies of 43% and 47%, which exhibit a gain of approximately 10 dB at 0.8 GHz and 2.1 GHz, respectively.

scholarly journals Machine-Learning Assisted Optimisation of Free-Parameters of a Dual-Input Power Amplifier for Wideband Applications

Sensors ◽  
2021 ◽  
Vol 21 (8) ◽  
pp. 2831
Author(s):  
Teng Wang ◽  
Wantao Li ◽  
Roberto Quaglia ◽  
Pere L. Gilabert
Keyword(s):  
Power Amplifier ◽  
Power Efficiency ◽  
Average Power ◽  
Long Term Evolution ◽  
Input Power ◽  
Global Optimisation ◽  
Power Ratio ◽  
Term Evolution ◽  
Free Parameters

This paper presents an auto-tuning approach for dual-input power amplifiers using a combination of global optimisation search algorithms and adaptive linearisation in the optimisation of a multiple-input power amplifier. The objective is to exploit the extra degrees of freedom provided by dual-input topologies to enhance the power efficiency figures along wide signal bandwidths and high peak-to-average power ratio values, while being compliant with the linearity requirements. By using heuristic search global optimisation algorithms, such as the simulated annealing or the adaptive Lipschitz Optimisation, it is possible to find the best parameter configuration for PA biasing, signal calibration, and digital predistortion linearisation to help mitigating the inherent trade-off between linearity and power efficiency. Experimental results using a load-modulated balanced amplifier as device-under-test showed that after properly tuning the selected free-parameters it was possible to maximise the power efficiency when considering long-term evolution signals with different bandwidths. For example, a carrier aggregated a long-term evolution signal with up to 200 MHz instantaneous bandwidth and a peak-to-average power ratio greater than 10 dB, and was amplified with a mean output power around 33 dBm and 22.2% of mean power efficiency while meeting the in-band (error vector magnitude lower than 1%) and out-of-band (adjacent channel leakage ratio lower than −45 dBc) linearity requirements.

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

scholarly journals An 0.4–2.8 GHz CMOS Power Amplifier With On-Chip Broadband-Pre-Distorter (BPD) Achieving 36.1–38.6% PAE and 21 dBm Maximum Linear Output Power

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 48831-48840
Author(s):  
Selvakumar Mariappan ◽  
Jagadheswaran Rajendran ◽  
Yusman M. Yusof ◽  
Norlaili M. Noh ◽  
Binboga Siddik Yarman
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
On Chip

Fully-integrated GaAs HBT power amplifier MMIC with high linear output power for 3 GHz-band broadband wireless applications

2006 ◽  
Vol 42 (22) ◽  
pp. 1286 ◽  
Author(s):  
M. Hirata ◽  
T. Oka ◽  
M. Hasegawa ◽  
Y. Amano ◽  
Y. Ishimaru ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Broadband Wireless ◽  
Fully Integrated ◽  
Wireless Applications
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