A 2GSPS 8-bit ADC with digital foreground calibration technology

Author(s):  
Zheng-Ping Zhang ◽  
Yong-Lu Wang ◽  
Xin-Fa Huang
2021 ◽  
Vol 503 (1) ◽  
pp. 344-353
Author(s):  
Emma Shen ◽  
Dominic Anstey ◽  
Eloy de Lera Acedo ◽  
Anastasia Fialkov ◽  
Will Handley

ABSTRACT We modelled the two major layer of Earth’s ionosphere, the F-layer and the D-layer, by a simplified spatial model with temporal variance to study the chromatic ionospheric effects on global 21-cm observations. From the analyses, we found that the magnitude of the ionospheric disruptions due to ionospheric refraction and absorption can be greater than the expected global 21-cm signal, and the variation of its magnitude can differ, depending on the ionospheric conditions. Within the parameter space adopted in the model, the shape of the global 21-cm signal is distorted after propagating through the ionosphere, while its amplitude is weakened. It is observed that the ionospheric effects do not cancel out over time, and thus should be accounted for in the foreground calibration at each timestep to account for the chromaticity introduced by the ionosphere.


IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 172467-172480
Author(s):  
Qihui Zhang ◽  
Ning Ning ◽  
Jing Li ◽  
Qi Yu ◽  
Kejun Wu ◽  
...  

2019 ◽  
Vol 28 (03) ◽  
pp. 1950045
Author(s):  
Maliang Liu ◽  
Sirui Zhang ◽  
Hu Jin ◽  
Zhangming Zhu ◽  
Yintang Yang

A low complexity all-digital foreground calibration technique to correct linear and nonlinear errors is proposed for pipeline ADCs in this paper. This method based on the integral nonlinearity (INL) piecewise least-squares fitting improves the linearity and obtains better SNR and SFDR performance. Two switches are added to the pre-stage reference ladder to achieve an accurate measurement of the INL and DNL of the backend ADC, which reduces the calibration complexity and improves the linearity effectively. The method was applied to a 125[Formula: see text]MS/s 14-bit pipeline ADC fabricated in a 0.18[Formula: see text][Formula: see text]m CMOS process. The raw DNL and INL were 1[Formula: see text]LSB and 8[Formula: see text]LSB, respectively, without calibration, but with calibration, they were respectively improved to 0.25[Formula: see text]LSB and 2[Formula: see text]LSB. The ADC achieved an SNR of 64.5[Formula: see text]dB, an SFDR of 73.8[Formula: see text]dB and a THD of 72.7[Formula: see text]dB with a 10[Formula: see text]MHz input signal without calibration, but after calibration these figures were improved to 72.6[Formula: see text]dB, 87.5[Formula: see text]dB and 86.6[Formula: see text]dB, respectively. Its application can also be extended to SAR ADC architecture, etc.


2020 ◽  
Vol 17 (10) ◽  
pp. 20200097-20200097
Author(s):  
Zhenwei Zhang ◽  
Lei Qiu ◽  
Yi Shan ◽  
Yemin Dong

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