Design of a 4 GS/s radix-1.75 single channel pipeline ADC in 28 nm CMOS technology with foreground calibration

A single channel 2 GSps, 8-bit folding and interpolation (F&I) analog-to-digital converter (ADC) with foreground calibration in TSMC 90 nm CMOS technology is presented in this paper. The ADC utilizes cascaded folding, which incorporates an interstage sample-and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A master-slave track-and-hold amplifier (THA) with bootstrapped switch is taken as the front-end circuit to improve ADC’s performance. The foreground digital assisted calibration has also been employed to correct the error of zero-crossing point caused by the circuit offset, thus improving the linearity of the ADC. Chip area of the whole ADC including pads is 930 μm × 930 μm. Postsimulation results demonstrate that, under a single supply of 1.2 volts, the power consumption is 210 mW. For the sampling rate of 2 GSps, the signal to noise and distortion ratio (SNDR) is 45.93 dB for Nyquist input signal.

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A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2017.2747758 ◽

2017 ◽

Vol 52 (12) ◽

pp. 3204-3218 ◽

Cited By ~ 33

Author(s):

Siddharth Devarajan ◽

Larry Singer ◽

Dan Kelly ◽

Tao Pan ◽

Jose Silva ◽

...

Keyword(s):

Cmos Technology ◽

Pipeline Adc ◽

28 Nm

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The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

Applied Sciences ◽

10.3390/app11010429 ◽

2021 ◽

Vol 11 (1) ◽

pp. 429

Author(s):

Min-Su Kim ◽

Youngoo Yang ◽

Hyungmo Koo ◽

Hansik Oh

Keyword(s):

Integrated Circuits ◽

Embedded System ◽

Low Power ◽

High Speed ◽

Cmos Technology ◽

Clock Frequency ◽

Clock Generation ◽

Allocation Method ◽

Evaluation Board ◽

28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078720001087 ◽

2020 ◽

pp. 1-18

Author(s):

Florent Torres ◽

Eric Kerhervé ◽

Andreia Cathelin ◽

Magali De Matos

Keyword(s):

Power Amplifier ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Fully Depleted ◽

Technology Roadmap ◽

Wide Range ◽

28 Nm ◽

Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

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