Physical and Electrical Characterization of Deep Trench Isolation in Bulk Silicon and SOI Substrates

2021 ◽  
Author(s):  
Moshe Agam ◽  
Rick Jerome ◽  
Lahcen Boukhanfra ◽  
Masaichi Eda ◽  
Lan Su ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Bulk Silicon ◽  
Deep Trench ◽  
Trench Isolation ◽  
Soi Substrates

scholarly journals Electrical Characterization of the Backside Interface on BSI Global Shutter Pixels with Tungsten-Shield Test Structures on CDTI Process

Sensors ◽  
2020 ◽  
Vol 20 (1) ◽  
pp. 287
Author(s):  
Célestin Doyen ◽  
Stéphane Ricq ◽  
Pierre Magnan ◽  
Olivier Marcelot ◽  
Marios Barlas ◽  
...  
Keyword(s):  
Dark Current ◽  
Electrical Characterization ◽  
Image Sensors ◽  
Density Of State ◽  
Deep Trench ◽  
Cmos Image Sensors ◽  
Trench Isolation ◽  
Key Factor

A new methodology is presented using well known electrical characterization techniques on dedicated single devices in order to investigate backside interface contribution to the measured pixel dark current in BSI CMOS image sensors technologies. Extractions of interface states and charges within the dielectric densities are achieved. The results show that, in our case, the density of state is not directly the source of dark current excursions. The quality of the passivation of the backside interface appears to be the key factor. Thanks to the presented new test structures, it has been demonstrated that the backside interface contribution to dark current can be investigated separately from other sources of dark current, such as the frontside interface, DTI (deep trench isolation), etc.

Electrical Characterization of the Access Transistor of Deep Trench Based DRAM Products via Backside Contacting

2004 ◽  
Author(s):  
Werner Lehner ◽  
Siegfried Pauthner ◽  
Herbert Radeck ◽  
Udo Weber ◽  
Jérôme Touzel
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Electrical Characterization ◽  
Access Memory ◽  
Deep Trench ◽  
Drain Side ◽  
The One ◽  
Basis Structure

Abstract Dynamic Random Access Memory (DRAM) is the one most widespread commodity product of the microelectronic industry. Although the basis structure is quite simple, an indepth electrical characterization of the single cell is mostly correlated with huge efforts in terms of test patterns due to the multiple possibilities for leakage of the cell itself [1]. A direct characterization of the access transistor is not possible because of the missing contact on the drain side (Deep Trench side). A tentative method to overcome this problem has been reported by G. Zimmermann, by using a front side Focused Ion Beam (FIB) contact to access the drain [2]. Unfortunately this method is limited to “coarse” technologies down to 0.15µm due to the resolution of the FIB probe. In addition, the backside contacting via trench allows the measurement of resistance and/or leakage elements at the interface buried strap, Poly 1-Poly 2 within DT (process conditioned). This paper presents an innovative way to contact the access transistor from the backside of the die, using the deep trench of the cell itself as connection to the drain of the investigated device. The backside contact to the polysilicon filled DT is the key aspect of the method and is realised by backside Focused Ion Beam.

Challenges of Atomic Force Probe Characterization of Logic Based Embedded DRAM for On-Processor Applications

2007 ◽  
Author(s):  
Terence Kane ◽  
Michael P. Tenney ◽  
Andrew Erickson ◽  
Sebastien Phan
Keyword(s):  
Electrical Characterization ◽  
Deep Trench ◽  
Atomic Force ◽  
Processor Designs ◽  
Measurement Methodology ◽  
Probe Placement

Abstract Nanoprobing logic based SOI embedded DRAM cells for on-processor designs poses different challenges than probing conventional six transistor SRAM designs. This paper will describe nanoprobing logic based embedded DRAM (eDRAM) cells in 65nm SOI applications. We will also describe probe placement and measurement methodology for electrical characterization of leakage between deep trench capacitors composing those eDRAM designs. The introduction of nano CV metrology and scanning capacitance imaging for use in characterizing DRAM capacitors will also be discussed.

Electrical characterization of SOI substrates incorporating WSi/sub x/ ground planes

2005 ◽  
Vol 26 (2) ◽  
pp. 72-74 ◽  
Author(s):  
M. Bain ◽  
M. Jin ◽  
S.H. Loh ◽  
P. Baine ◽  
B.M. Armstrong ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Soi Substrates

Electrical characterization of 12 nm EJ-MOSFETs on SOI substrates

2004 ◽  
Vol 48 (5) ◽  
pp. 739-745 ◽  
Author(s):  
W. Henschel ◽  
T. Wahlbrink ◽  
Y.M. Georgiev ◽  
M. Lemme ◽  
T. Mollenhauer ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Soi Substrates

SILICON NANOWIRES FORMATION IN CMOS COMPATIBLE MANNER

2006 ◽  
Vol 05 (04n05) ◽  
pp. 445-451 ◽  
Author(s):  
AJAY AGARWAL ◽  
N. BALASUBRAMANIAN ◽  
N. RANGANATHAN ◽  
R. KUMAR
Keyword(s):  
Silicon Nanowires ◽  
Silicon Nanowire ◽  
Electrical Characterization ◽  
Single Electron Transistor ◽  
Bulk Silicon ◽  
Nanowire Diameter ◽  
Section Shape ◽  
Medical Sensors ◽  
Cmos Compatible

We present CMOS compatible fabrication technique for silicon nanowire ( SiNW ) on bulk silicon wafers. Our method uses saw-tooth etch-profiles of fins followed by self-limiting oxidation to form vertically self-aligned horizontal SiNW down to 5 nm diameter. The concept of modifying the cross-section shape of SiNW from triangular to circular and the ability to achieve desired nanowire diameter are unique in this work. Nanowires formed by such technique can be utilized to realize several nanoelectronics devices like gate-all-around transistor, single-electron-transistor, etc.; NEMS and bio-medical sensors; all in a CMOS friendly manner. The physical and electrical characterization of the SiNW is also presented in this paper.

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