Electrical Characterization of the Access Transistor of Deep Trench Based DRAM Products via Backside Contacting

Author(s):  
Werner Lehner ◽  
Siegfried Pauthner ◽  
Herbert Radeck ◽  
Udo Weber ◽  
Jérôme Touzel

Abstract Dynamic Random Access Memory (DRAM) is the one most widespread commodity product of the microelectronic industry. Although the basis structure is quite simple, an indepth electrical characterization of the single cell is mostly correlated with huge efforts in terms of test patterns due to the multiple possibilities for leakage of the cell itself [1]. A direct characterization of the access transistor is not possible because of the missing contact on the drain side (Deep Trench side). A tentative method to overcome this problem has been reported by G. Zimmermann, by using a front side Focused Ion Beam (FIB) contact to access the drain [2]. Unfortunately this method is limited to “coarse” technologies down to 0.15µm due to the resolution of the FIB probe. In addition, the backside contacting via trench allows the measurement of resistance and/or leakage elements at the interface buried strap, Poly 1-Poly 2 within DT (process conditioned). This paper presents an innovative way to contact the access transistor from the backside of the die, using the deep trench of the cell itself as connection to the drain of the investigated device. The backside contact to the polysilicon filled DT is the key aspect of the method and is realised by backside Focused Ion Beam.

Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
P.K. Tan ◽  
Y.W. Goh ◽  
J.L. Cai ◽  
...  

Abstract As electronic devices shrink further in the nanometer regime, electrical characterization using nanoprobing has become increasingly important. Focused ion beam (FIB) is one useful technique that can be used to create markings for ease of defective site identification during nanoprobing. This paper investigates the impact of FIB exposure on the electrical parameters of the pull-up (PU), pull-down (PD) and pass-gate (PG) transistors of 6-Transistor Static Random Access Memory (6T SRAM) cells.


Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.


2003 ◽  
Vol 16 (2) ◽  
pp. 199-206 ◽  
Author(s):  
S. Smith ◽  
A.J. Walton ◽  
S. Bond ◽  
A.W.S. Ross ◽  
J. Tom ◽  
...  

Author(s):  
Steven B. Herschbein ◽  
Hyoung H. Kang ◽  
Harvey E. Berman ◽  
Carmelo F. Scrudato ◽  
Aaron D. Shore ◽  
...  

Abstract The presence of a full wafer dual-beam FIB on the process floor gave rise to an environment in which formerly segregated off-line lab and FAB tasks could be linked. One such idea involved a methodology for semi-automated defect targeting based on the spatial predictions of static random access memory (SRAM) electrical testing. The embedded memory blocks on some processors are fully configured and probe pad testable as early as the forth metal level. Using a unique navigation technique that combines electrically sorted SRAM bit map data with CAD coordinate information and stage driven X-Y stepping, the FIB tool was used to locate, section and image prior level defects. We believe that with the inclusion of suitable fiducial markers in the chip design and advanced pattern recognition to aid navigation and guide depth milling, a fully automated process for electrical yield detractor diagnosis could be introduced.


Nanopages ◽  
2006 ◽  
Vol 1 (2) ◽  
pp. 255-262 ◽  
Author(s):  
E. Horváth ◽  
P. L. Neumann ◽  
A. L. Tóth ◽  
É. Vázsonyi ◽  
A. A. Koós ◽  
...  

2003 ◽  
Vol 47 (10) ◽  
pp. 1641-1644 ◽  
Author(s):  
D. Deleruyelle ◽  
J. Cluzel ◽  
B. De Salvo ◽  
D. Fraboulet ◽  
D. Mariolle ◽  
...  

1995 ◽  
Vol 34 (Part 1, No. 9B) ◽  
pp. 5178-5183 ◽  
Author(s):  
Cheol Seong Hwang ◽  
Soon Oh Park ◽  
Chang Seok Kang ◽  
Hag-Ju Cho ◽  
Ho-Kyu Kang ◽  
...  

2007 ◽  
Vol 121-123 ◽  
pp. 591-594
Author(s):  
Bo Liu ◽  
Zhi Tang Song ◽  
Song Lin Feng ◽  
Bomy Chen

Nano-cell-elements of chalcogenide random access memory (C-RAM) based on Ge2Sb2Te5 films have been successively fabricated by using the focused ion beam method. The minimum contact size between the Ge2Sb2Te5 phase change film and bottom electrode film in the nano-cell-element is in diameter of 90nm. The current-voltage characteristics of the C-RAM cell element are studied using the home-made current-voltage tester in our laboratory. The minimum SET current of about 0.3mA is obtained.


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