SILICON NANOWIRES FORMATION IN CMOS COMPATIBLE MANNER

2006 ◽  
Vol 05 (04n05) ◽  
pp. 445-451 ◽  
Author(s):  
AJAY AGARWAL ◽  
N. BALASUBRAMANIAN ◽  
N. RANGANATHAN ◽  
R. KUMAR
Keyword(s):  
Silicon Nanowires ◽  
Silicon Nanowire ◽  
Electrical Characterization ◽  
Single Electron Transistor ◽  
Bulk Silicon ◽  
Nanowire Diameter ◽  
Section Shape ◽  
Medical Sensors ◽  
Cmos Compatible

We present CMOS compatible fabrication technique for silicon nanowire ( SiNW ) on bulk silicon wafers. Our method uses saw-tooth etch-profiles of fins followed by self-limiting oxidation to form vertically self-aligned horizontal SiNW down to 5 nm diameter. The concept of modifying the cross-section shape of SiNW from triangular to circular and the ability to achieve desired nanowire diameter are unique in this work. Nanowires formed by such technique can be utilized to realize several nanoelectronics devices like gate-all-around transistor, single-electron-transistor, etc.; NEMS and bio-medical sensors; all in a CMOS friendly manner. The physical and electrical characterization of the SiNW is also presented in this paper.

Fabrication of silicon nanowire network in aluminum thin films

2005 ◽  
Vol 862 ◽  
Author(s):  
Vincent H. Liu ◽  
Husam H. Abu-Safe ◽  
Hameed A. Naseem ◽  
William D. Brown
Keyword(s):  
Thin Film ◽  
Silicon Nanowires ◽  
Silicon Nanowire ◽  
Vertical Direction ◽  
X Ray ◽  
Nanowire Network ◽  
Aluminum Thin Film ◽  
Nanowire Networks ◽  
Scanning Electron

AbstractThe formation of isolated silicon nanowires and silicon nanowire networks using aluminum thin film is investigated. The formation mechanism of the network mainly depends on the diffusion of silicon in the aluminum thin film. The silicon stops at the film grain boundaries. The continuous accumulations of silicon at these boundaries give raise to a continuous network of silicon nanowires. Characterization of the nanowires has been done using scanning electron microscopy and energy dispersive x-ray spectroscopy. These results are unique in the fact that the nanowires found are grown in a horizontal fashion instead of the more common vertical direction. Most of the nanowires have a diameter of about 60 nm and a length of over 10 μm.

Characterizing the Two-Dimensional Doping Concentration inside Silicon-Nanowires Using Scanning Spreading Resistance Microscopy

2009 ◽  
Vol 1178 ◽  
Author(s):  
Thomas Hantschel ◽  
Volker Schulz ◽  
Andreas Schulze ◽  
Esteban Angeletti ◽  
Firat Guder ◽  
...  
Keyword(s):  
Silicon Nanowires ◽  
Silicon Nanowire ◽  
Electronic Devices ◽  
Longitudinal Axis ◽  
Two Dimensional ◽  
Electrical Measurements ◽  
Spreading Resistance ◽  
Sectioning Method ◽  
Etched Silicon

AbstractThe characterization of doped regions inside silicon nanowire structures poses a challenge which must be overcome if these structures are to be incorporated into future electronic devices. Precise cross-sectioning of the nanowire along its longitudinal axis is required, followed by two-dimensional electrical measurements with nanometer spatial resolution. The authors have developed an approach to cross-section silicon nanowires and to characterize them by scanning spreading resistance microscopy (SSRM). This paper describes a cleaving- and polishing-based cross-sectioning method for silicon nanowires. High resolution SSRM measurements are demonstrated for epitaxially grown and etched silicon nanowires.

ELECTRICAL CHARACTERIZATION OF PLANAR SILICON NANOWIRE FIELD-EFFECT TRANSISTORS

2012 ◽  
Vol 11 (04) ◽  
pp. 1240011
Author(s):  
G. ROSAZ ◽  
B. SALEM ◽  
N. PAUC ◽  
P. GENTILE ◽  
A. POTIÉ ◽  
...  
Keyword(s):  
Silicon Nanowires ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Electrical Characterization ◽  
Hysteretic Behavior ◽  
Oxide Shell ◽  
Back Gate ◽  
Voltage Sweep

Silicon nanowires (Si NWs) are promising candidates for field-effect transistor (FET) conduction channel. Planar configuration using a back gate is an easy way to study these devices. We demonstrate the possibility to build high performance FET using a simple silicidation process leading to high effective holes' mobility between 130 cm2⋅V-1⋅s-1 and 200 cm2⋅V-1⋅s-1 and good ION/IOFF ratio up to 105. Moreover we investigated the possibility to passivate the NWs using either a high-k dielectric layer or a thermal oxide shell around the NWs. This leads to a reduction of the hysteretic behavior during the gate voltage sweep from 30 V to 1 V depending on the material and the gate configuration.

Silicon Nanowire Electromechanical Switch for Logic Device Application

2007 ◽  
Vol 1018 ◽  
Author(s):  
Qiliang Li ◽  
Sang-Mo Koo ◽  
Monica D. Edelstein ◽  
John S. Suehle ◽  
Curt A. Richter
Keyword(s):  
Silicon Nanowires ◽  
Silicon Nanowire ◽  
Chemical Vapor ◽  
Metal Electrode ◽  
Subthreshold Slope ◽  
Logic Device ◽  
Metal Electrodes ◽  
Device Application ◽  
Switching Characteristics

AbstractIn this paper, we have reported the fabrication and characterization of nanowire electromechanical switches consisting of chemical-vapor-deposition grown silicon nanowires suspended over metal electrodes. The devices operate as transistors with the suspended part of the nanowire bent to touch metal electrode via electromechanical force by applying voltage. The reversible switching, large on/off current ratio, small subthreshold slope and low switching energy compared to current CMOSFET make the switches very attractive for logic device application. In addition, we have developed a physical model to investigate the switching characteristics and extract the material properties.

scholarly journals Silicon Nanowires: A Breakthrough for Thermoelectric Applications

Materials ◽  
2021 ◽  
Vol 14 (18) ◽  
pp. 5305
Author(s):  
Giovanni Pennelli ◽  
Elisabetta Dimaggio ◽  
Antonella Masci
Keyword(s):  
Integrated Circuits ◽  
Power Factor ◽  
Silicon Nanowires ◽  
Silicon Nanowire ◽  
Large Temperature ◽  
Nanowire Diameter ◽  
Large Numbers ◽  
High Power Factor ◽  
Experimental Works ◽  
Very High

The potentialities of silicon as a starting material for electronic devices are well known and largely exploited, driving the worldwide spreading of integrated circuits. When nanostructured, silicon is also an excellent material for thermoelectric applications, and hence it could give a significant contribution in the fundamental fields of energy micro-harvesting (scavenging) and macro-harvesting. On the basis of recently published experimental works, we show that the power factor of silicon is very high in a large temperature range (from room temperature up to 900 K). Combining the high power factor with the reduced thermal conductivity of monocrystalline silicon nanowires and nanostructures, we show that the foreseen figure of merit ZT could be very high, reaching values well above 1 at temperatures around 900 K. We report the best parameters to optimize the thermoelectric properties of silicon nanostructures, in terms of doping concentration and nanowire diameter. At the end, we report some technological processes and solutions for the fabrication of macroscopic thermoelectric devices, based on large numbers of silicon nanowire/nanostructures, showing some fabricated demonstrators.

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