Simulation Study of the Use of AlGaN/GaN Ultra-Thin-Barrier HEMTs with Hybrid Gates for Achieving a Wide Threshold Voltage Modulation Range

In this work, novel hybrid gate Ultra-Thin-Barrier HEMTs (HG-UTB HEMTs) featuring a wide modulation range of threshold voltages (VTH) are proposed. The hybrid gate structure consists of a p-GaN gate part and a MIS-gate part. Due to the depletion effect assisted by the p-GaN gate part, the VTH of HG-UTB HEMTs can be significantly increased. By tailoring the hole concentration of the p-GaN gate, the VTH can be flexibly modulated from 1.63 V to 3.84 V. Moreover, the MIS-gate part enables the effective reduction in the electric field (E-field) peak at the drain-side edge of the p-GaN gate, which reduces the potential gate degradation originating from the high E-field in the p-GaN gate. Meanwhile, the HG-UTB HEMTs exhibit a maximum drain current as high as 701 mA/mm and correspond to an on-resistance of 10.1 Ω mm and a breakdown voltage of 610 V. The proposed HG-UTB HEMTs are a potential means to achieve normally off GaN HEMTs with a promising device performance and featuring a flexible VTH modulation range, which is of great interest for versatile power applications.

Enhanced Reverse Recovery Performance in Superjunction MOSFET with Reduced Hole-Barrier

High reverse recovery charge (QRR) and resultant high switching losses have become the main factors that constrain the performance and application area of superjunction MOSFET (SJ-MOSFET). To reduce QRR, an SJ-MOSFET with reduced hole-barrier is proposed and demonstrated. By introducing a Schottky contact on the bottom of the n-pillar at the drain side, the barrier for the hole carrier is dramatically reduced in the reverse conduction state. As a result, the hole carrier in the drift region is significantly reduced, which results in a low QRR and enhanced reverse recovery performance. Compared with the conventional SJ-MOSFET (Conv-SJ-MOSFET), the proposed device achieves 64.6% lower QRR with almost no sacrifice in other characteristics. The attenuated QRR accounts for a 19.6% ~ 46.8% reduction in total power losses with operation frequency at 5 ~ 200 kHz, demonstrating the great potential of the proposed SJ-MOSFET used in power conversion systems.

LoGHeD: An effective approach for negative differential resistance effect suppression in negative capacitance transistors

A negative capacitance transistor (NCFET) with fully depleted silicon-on-insulator (FDSOI) technology (NC-FDSOI) is one of the promising candidates for next-generation low-power devices. However, it suffers from the inherent negative differential resistance (NDR) effect, which is very detrimental to device and circuit designs. Aiming at overcoming this shortcoming, this paper proposes for the first time to use local Gaussian heavy doping technology (LoGHeD) in the channel near the drain side to suppress the NDR effect in the NC-FDSOI. The technical computer-aided design (TCAD) simulation results have validated that the output conductance (GDS) with LoGHeD, which is used to measure the NDR effect, increases compared to the conventional NC-FDSOI counterpart and approaches zero. With the increase in doping concentration, the inhibitory capability of the NDR effect shows a monotonously increasing trend. In addition, the proposed approach maintains and even enhances performances of the NC-FDSOI transistor regarding the electrical parameters, such as threshold voltage (VTH), sub-threshold swing (SS), switching current ratio (ION/IOFF), and drain-induced barrier lowering (DIBL).

Impact of Gate Offset in Gate Recess on DC and RF Performance of InAlAs/InGaAs InP-based HEMTs

In this work, a set of 100-nm gate-length InP-based HEMTs were designed and fabricated with different gate offsets in gate recess. A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam lithography. DC and RF measurement was conducted. With the gate offset varying from drain side to source side, the maximum drain current (Ids,max) and transconductance (gm,max) increased. In the meantime, f T decreased while f max increased, and the highest f max of 1096 GHz was obtained. It can be explained by the increase of gate-source capacitance and the decrease of gate-drain capacitance and source resistance. Output conductance was also suppressed by gate offset toward source side. This provides simple and flexible device parameter selection for HEMTs of different usage.

Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (LG). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (AR). The physical variants in this work are symmetric spacer length (LSD), source side spacer length (LS) and drain side spacer length (LD). The simulation results give highest ION/IOFF ratio with LD variation compared to LS and LSD, whereas latter two variations have similar effect on ION/IOFF ratio. At 25 nm (2.5 × LG) of LD, the device gives appreciable ON current with the highest ION/IOFF ratio (2.19 × 108) with optimum subthreshold slope (SS) and ensures low power and high switching drivability. Moreover, it is noticed that among optimal values of LS and LD, the device ION/IOFF ratio has an improvement of 22.69% as compared to other variations. Moreover, the effect of various spacer dielectrics on optimized device is also investigated. Finally, the CMOS inverter circuit analysis is performed on the optimized symmetric and asymmetric spacer lengths.

Leakage Mitigation in NW FET using Negative Schottky Junction Drain and its Process Variation Analysis

In this work, a Schottky junction on the drain side employing low workfunction (WF) metal is proposed as a method to suppress the OFF-state leakage in nanowire (NW) field-effect transistor (FET). Instead of a highly n+ doped drain, low WF metal with negative electron Schottky-barrier height (SBH) as a drain minimizes the lateral band-to-band tunneling (L-BTBT) considerably. L-BTBT is the movement of carriers (holes) from the drain conduction band (CB) into the channel valence band (VB) during the OFF-state. Impact of varying WF at channel-drain junction on the device characteristics is studied. It is observed that SBH60 eV is required to mitigate L-BTBT compared to the conventionally-doped and junctionless (JL) NW counterpart. Furthermore, unlike L-BTBT, leakage in NW Schottky-drain (SD) comprises of holes tunneling through the SB from the metal drain into the channel and termed as the lateral SB tunneling (L-SBT). In contrast to JL NW FET, the process variation immunity (varying channel doping, NCh and NW diameter, dNW ) and the ON-state current of the proposed device is not compromised at the expense of lower OFF-state LSBT. Instead, the device is less susceptible to process variations and retains the ON-state performance of the NW MOSFET. For a ±20% change in NCh, ∆IOF F /IOF F of 7% compared to 97% in NW JL FET is observed.