We present novel test set encoding and pattern decompression methods for core-based
systems. These are based on the use of twisted-ring counters and offer a number of
important advantages–significant test compression (over 10X in many cases), less tester
memory and reduced testing time, the ability to use a slow tester without compromising
test quality or testing time, and no performance degradation for the core under test.
Surprisingly, the encoded test sets obtained from partially-specified test sets (test cubes)
are often smaller than the compacted test sets generated by automatic test pattern
generation programs. Moreover, a large number of patterns are applied test-per-clock to
cores, thereby increasing the likelihood of detecting non-modeled faults. Experimental
results for the ISCAS benchmark circuits demonstrate that the proposed test
architecture offers an attractive solution to the problem of achieving high test quality
and low testing time with relatively slower, less expensive testers.
An Efficient Test Pattern Generation Scheme for an On Chip BIST