A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process

2008 ◽  
Author(s):  
Pratap Narayan Singh ◽  
Ashish Kumar ◽  
Chandrajit Debnath ◽  
Rakesh Malik
Keyword(s):  
Cmos Process ◽  
Digital Cmos ◽  
Time Interleaved

scholarly journals NANO-studio, the design environment of filter banks implemented in standard CMOS technology

2021 ◽  
Author(s):  
Andrzej Handkiewicz ◽  
Mariusz Naumowicz
Keyword(s):  
Impulse Response ◽  
Filter Banks ◽  
Finite Impulse Response ◽  
Infinite Impulse Response ◽  
Cmos Process ◽  
Digital Cmos ◽  
Additional Advantage ◽  
Analysis And Synthesis ◽  
Optimization Parameters ◽  
Synthesis Filter

AbstractThe paper presents a method of optimizing frequency characteristics of filter banks in terms of their implementation in digital CMOS technologies in nanoscale. Usability of such filters is demonstrated by frequency-interleaved (FI) analog-to-digital converters (ADC). An analysis filter present in these converters was designed in switched-current technique. However, due to huge technological pitch of standard digital CMOS process in nanoscale, its characteristics substantially deviate from the required ones. NANO-studio environment presented in the paper allows adjustment, with transistor channel sizes as optimization parameters. The same environment is used at designing a digital synthesis filter, whereas optimization parameters are input and output conductances, gyration transconductances and capacitances of a prototype circuit. Transition between analog s and digital z domains is done by means of bilinear transformation. Assuming a lossless gyrator-capacitor (gC) multiport network as a prototype circuit, both for analysis and synthesis filter banks in FI ADC, is an implementation of the strategy to design filters with low sensitivity to parameter changes. An additional advantage is designing the synthesis filter as stable infinite impulse response (IIR) instead of commonly used finite impulse response (FIR) filters. It provides several dozen-fold saving in the number of applied multipliers.. The analysis and synthesis filters in FI ADC are implemented as filter pairs. An additional example of three-filter bank demonstrates versatility of NANO-studio software.

Design Methodologies for Low-Power CMOS Operational Amplifiers in a 0.25¿m Digital CMOS Process

2006 ◽  
Author(s):  
Alfonso Cesar B. Albason ◽  
Neil Michael L. Axalan ◽  
Maria Theresa A. Gusad ◽  
John Richard E. Hizon ◽  
Marc D. Rosales
Keyword(s):  
Low Power ◽  
Operational Amplifiers ◽  
Cmos Process ◽  
Digital Cmos ◽  
Design Methodologies ◽  
Low Power Cmos ◽  
Cmos Operational Amplifiers

scholarly journals Transceiver with inductive coupling for wireless chip-to-chip communication using a 50-nm digital CMOS process

2013 ◽  
Vol 44 (9) ◽  
pp. 852-859 ◽  
Author(s):  
Changhyun Lee ◽  
Jonghoon Park ◽  
Jinho Yoo ◽  
Hyungjun Cho ◽  
Jungi Choi ◽  
...  
Keyword(s):  
Inductive Coupling ◽  
Cmos Process ◽  
Digital Cmos

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones

2005 ◽  
Vol 40 (11) ◽  
pp. 2203-2211 ◽  
Author(s):  
R.B. Staszewski ◽  
Chih-Ming Hung ◽  
N. Barton ◽  
Meng-Chang Lee ◽  
D. Leipold
Keyword(s):  
Mobile Phones ◽  
Cmos Process ◽  
Digital Cmos ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator
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