Multi-level electro-thermal modeling for circuit simulation of packaged power devices

Author(s):  
A. Castellazzi ◽  
M. Ciappa
2021 ◽  
Vol 2125 (1) ◽  
pp. 012051
Author(s):  
Guoqing Qiu ◽  
Kedi Jiang ◽  
Shengyou Xu ◽  
Xin Yang ◽  
Wei Wang

Abstract Although the superior performance of SiC MOSFET devices has beenvalidated by many studies, it is necessary to overcome many technical bottlenecks to make SiC MOSFET gradually replace Si-based power devices into the mainstream. In view of the current situation where the performance of SiC MOSFETs in power conversion devices cannot be evaluated well at this stage, it is necessary to carry out fine modeling of SiC MOSFETs and establish accurate simulation models. In this paper, the powerful mathematical processing capability and rich modules of Matlab/Simulink are used to build a SiC MOSFET model, and then the product data sheet is compared with the fitted data. The results show that the switching simulation waveforms are in general agreement with the data sheet waveforms, and the error is less than 7%. Verifing the accuracy of the model and reducing the difficulty of modeling, it provides a new idea for establishing the circuit simulation model of SiC MOSFET in Matlab/Simulink.


2019 ◽  
Vol 9 (16) ◽  
pp. 3240
Author(s):  
Wei ◽  
Cheng ◽  
Lu ◽  
Siwakoti ◽  
Zhang

In relation to power converter design, power density is increasing while the form factor isdecreasing. This trend generally reduces the rate of the cooling process, which increases the mutualthermal coupling among the surrounding power components. Most of the traditional modelsusually ignore the mutual effects or just focus on the conduction coupling. To deal with these factors,the thermal modeling for a boost converter system has been built to compare the junctiontemperatures (Tj) and the increments under different working conditions in order to consider theconduction coupling. A multi-variable thermal resistances model is proposed in this paper toincorporate the convection thermal coupling into the mutual thermal effects. The couplingresistances, MOSFET to the diode[...]


1999 ◽  
Vol 565 ◽  
Author(s):  
K. C. Yu ◽  
J. Defilippi ◽  
R. Tiwari ◽  
T. Sparks ◽  
D. Smith ◽  
...  

AbstractThe recent introduction of dual inlaid Cu and oxide based interconnects within sub-0.25μm CMOS technology has delivered higher performance and lower power devices. Further speed improvements and power reduction may be achieved by reducing the interconnect parasitic capacitance through integration of low-k interlevel dielectric (ILD) materials with Cu. This paper demonstrates successful multi-level dual inlaid Cu/low-k interconnects with ILD permittivities ranging from 2.0 to 2.5. Integration challenges specific to inorganic low-k and Cu based structures are discussed. Through advanced CMP process development, multi-level integration of porous oxide materials with moduli less than 0.5 GPa is demonstrated. Parametric data and isothermal annealing of these Cu/ low-k structures show results with yield comparable to Cu/oxide based interconnects.


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