Radiation Hardened High-Speed LVDS compliant Transceiver

2019 ◽  
Author(s):  
Niraj Kumar Jha ◽  
Dishank Yadav ◽  
Anuj Maheshwari ◽  
Mrigank Sharad
Keyword(s):  
High Speed ◽  
Radiation Hardened

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

Improved Soi Films By High Dose Oxygen Implantation and Lamp Annealing

1985 ◽  
Vol 53 ◽  
Author(s):  
G. K. Celler ◽  
P. L. F. Hemment ◽  
K. W. West ◽  
J. M. Gibson
Keyword(s):  
High Speed ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
High Dose ◽  
Cmos Circuits ◽  
Radiation Hardened ◽  
Silicon On Insulator Technology ◽  
Annealing Procedure ◽  
Oxygen Precipitates ◽  
Sharp Interfaces

ABSTRACTIon beam synthesis of a buried SiO2 layer is an attractive silicon-on-insulator technology for high speed CMOS circuits and radiation hardened devices. We demonstrate here a new annealing procedure at 1405°C that produces silicon films of excellent quality, essentially free of oxygen precipitates and with sharp interfaces between the Si and the SiO2.

Novel SOI-Specific circuit form high-speed radiation-hardened memories

2008 ◽  
Author(s):  
T.P. Haraszti ◽  
R. Pancholy ◽  
J. Chona ◽  
R. Schober ◽  
K. Hunt
Keyword(s):  
High Speed ◽  
Radiation Hardened

Low Power, High-Speed Radiation Hardened Computer & Flight Experiment

2005 ◽  
Author(s):  
D.R. Czajkowski ◽  
M.P. Pagey ◽  
P.K. Samudrala ◽  
M. Goksel ◽  
M.J. Viehman
Keyword(s):  
Low Power ◽  
High Speed ◽  
Flight Experiment ◽  
Radiation Hardened

Radiation Hardened High Speed Digitizer

2019 ◽  
Author(s):  
Robert Merl ◽  
Zachary Baker ◽  
Larry Casper ◽  
Chuck Clanton ◽  
Richard Dutch ◽  
...  
Keyword(s):  
High Speed ◽  
Radiation Hardened

scholarly journals A 112 Gb/s Radiation-Hardened Mid-Board Optical Transceiver in 130-nm SiGe BiCMOS for Intra-Satellite Links

2021 ◽  
Vol 9 ◽  
Author(s):  
Stavros Giannakopoulos ◽  
Ilias Sourikopoulos ◽  
Leontios Stampoulidis ◽  
Pylyp Ostrovskyy ◽  
Florian Teply ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Flip Chip ◽  
Cavity Surface ◽  
Sige Bicmos ◽  
Speed Performance ◽  
Vertical Cavity Surface ◽  
Transceiver Module ◽  
Radiation Hardened ◽  
Logic Cells

We report the design of a 112 Gb/s radiation-hardened (RH) optical transceiver applicable to intra-satellite optical interconnects. The transceiver chipset comprises a vertical-cavity surface-emitting laser (VCSEL) driver and transimpedance amplifier (TIA) integrated circuits (ICs) with four channels per die, which are adapted for a flip-chip assembly into a mid-board optics (MBO) optical transceiver module. The ICs are designed in the IHP 130 nm SiGe BiCMOS process (SG13RH) leveraging proven robustness in radiation environments and high-speed performance featuring bipolar transistors (HBTs) with fT/fMAX values of up to 250/340 GHz. Besides hardening by technology, radiation-hardened-by-design (RHBD) components are used, including enclosed layout transistors (ELTs) and digital logic cells. We report design features of the ICs and the module, and provide performance data from post-layout simulations. We present radiation evaluation data on analog devices and digital cells, which indicate that the transceiver ICs will reliably operate at typical total ionizing dose (TID) levels and single event latch-up thresholds found in geostationary satellites.

Thick Films for Dielectric Isolation by Lateral Epitaxy from the Melt

1983 ◽  
Vol 23 ◽  
Author(s):  
G. K. Celler ◽  
L. E. Trimble
Keyword(s):  
Grain Boundaries ◽  
High Voltage ◽  
High Speed ◽  
Wafer Fabrication ◽  
Regular Array ◽  
Radiation Hardened ◽  
Lateral Epitaxy ◽  
Si Films ◽  
Induced Defects ◽  
Low Capacitance

ABSTRACTDielectric Isolation (DI) technology has been available for almost twenty years. It was first developed for low capacitance, high speed circuits, and was later adapted to radiation hardened devices and for high voltage isolation. We describe a new method of forming DI structures that simplifies wafer fabrication, reduces the density of process induced defects, and may lead to a more flexible device design. Our process is based on recrystallization from the melt of thick Si films deposited over oxidized Si wafers, with a regular array of seeding windows opened in the isolation oxide. The recrystallized films are free of grain boundaries and subboundaries.

Sign in / Sign up

Export Citation Format

Share Document