Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

Precipitation in silicon-on-insulator material during high- temperature annealing

1987 ◽  
Vol 45 ◽  
pp. 254-255
Author(s):  
S. J. Krause ◽  
C. O. Jung ◽  
S.R. Wilson
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Annealing Time ◽  
High Speed ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Precipitate Size ◽  
High Dose ◽  
High Temperature Annealing ◽  
Implantation Energy

Silicon-on-insulator (SOI) structure by high dose oxygen implantation (SIMOX) has excellent potential for use in radiation hardened and high speed integrated circuits. Device fabrication in SIMOX requires a high quality superficial Si layer above the buried oxide layer. Previously we reported on the effect of heater temperature, background doping, and annealing cycle on precipitate size, density, and location in the superficial Si layer. Precipitates were not eliminated with our processing conditions, but various authors have recently reported that high temperature annealing of SIMOX, from 1250°C to 1405°C, eliminates virtually all precipitates in the superficial Si layer. However, in those studies there were significant differences in implantation energy and dose and also annealing time and temperature. Here we are reporting on the effect of annealing time and temperature on the formation and changes in precipitates.

An Overview of 300 mm SOI Starting Wafer Quality and Its Yield Detractors

2005 ◽  
Author(s):  
Pei Y. Tsai ◽  
Junedong Lee ◽  
Paul Ronsheim ◽  
Lindsay Burns ◽  
Richard Murphy ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Device Fabrication ◽  
Sampling Plan ◽  
Silicon On Insulator ◽  
Manufacturing Processes ◽  
Circuit Performance ◽  
Characterization Techniques ◽  
Wafer Manufacturing

Abstract A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

High-quality torque control at zero and very high speed operation

1995 ◽  
Vol 1 (4) ◽  
pp. 7-13 ◽  
Author(s):  
P.I. Jansen ◽  
C.O. Thompson ◽  
R.D. Lorenz
Keyword(s):  
High Speed ◽  
Torque Control ◽  
High Quality ◽  
Very High

III-V HETEROJUNCTION BIPOLAR TRANSISTORS FOR HIGH-SPEED APPLICATIONS

1990 ◽  
Vol 01 (03n04) ◽  
pp. 245-301 ◽  
Author(s):  
M.F. CHANG ◽  
P.M. ASBECK
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
High Speed ◽  
High Performance ◽  
Growth Parameters ◽  
Bipolar Transistors ◽  
System Requirements ◽  
Potential Impact ◽  
Computational Systems ◽  
Very High

Recent advances in communication, radar and computational systems demand very high performance electronic circuits. Heterojunction bipolar transistors (HBTs) have the potential of providing a more efficient solution to many key system requirements through intrinsic device advantages than competing technologies. This paper reviews the present status of GaAs and InP-based HBT technologies and their applications to digital, analog, microwave and multifunction circuits. It begins with a brief review of HBT device concepts and critical epitaxial growth parameters. Issues important for device modeling and fabrication technologies are discussed. The paper then highlights the performance and the potential impact of HBT devices and integrated circuits in various application areas. Key prospects for future HBT development are also addressed.

Evening Panel Session (November 16, 1983) Soi Technologies for Integrated Circuits

1983 ◽  
Vol 23 ◽  
Author(s):  
John C. C. Fan ◽  
Y. Akasaka ◽  
G. W. Cullen ◽  
J. F. Gibbons ◽  
C. Hill ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Density ◽  
Silicon On Insulator ◽  
Panel Session ◽  
Near Term

There are a number of viable approaches to silicon-on-insulator (SOI) technologies, and the panel session has assembled a number of leaders in the SOI community for their views of “SOI Technologies for Integrated Circuits.” Their viewpoints, shown in tabulated form, were presented for general discussion in the session which was attended by about 150 people. Although SOI technologies are useful for many applications, most of the panelists agreed that the most appropriate near-term applications are for high-speed, high-density integrated circuits. Various SOI technologies, including silicon-on-sapphire (SOS), are currently in the running, but the majority of the panelists felt that for SOI technologies to be widely adopted, SOI must be available as a proven manufactured product within two to three years.

Sign in / Sign up

Export Citation Format

Share Document