Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories

This paper presents novel multi-bit static random access memories (SRAMs) using spatial wave-function switched (SWS) FETs. A SWS-FET comprises of two or more vertically stacked quantum well channels while having a single gate and multiple sources and drains. Simulations are presented for 2-bit static random access memories (SRAMs) using cross-coupled 4-states SWS-CMOS inverters. The CMOS inverters are based on 4-state SWS FETs using two Si/SiGe quantum well channels. SWS-structures having 4-quantum well channels processing 8-states/3-bit are described. Logic simulation of multi-bit latches and registers is also presented. Multi-bit CMOS SWS-SRAMs and registers, integrated with logic, and quantum dot nonvolatile random access memories (QD-NVRAMs) presents a new paradigm for low power, high-speed computing.

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Low Power Restoration Circuits Reduce Swing Voltages of SRAM Cell With Improved Read and Write Margins

International Journal of Security and Privacy in Pervasive Computing ◽

10.4018/ijsppc.2021040102 ◽

2021 ◽

Vol 13 (2) ◽

pp. 16-28

Author(s):

Vinod Kumar ◽

Ram Murti Rawat

Keyword(s):

Comparative Analysis ◽

Low Power ◽

Random Access ◽

Noise Margin ◽

Sram Cell ◽

Static Random Access Memories ◽

Power Restoration ◽

Node Voltage ◽

Static Noise ◽

Better Than

This paper examines the factors that affect the static noise margin (SNM) of static random access memories which focus on optimizing read and write operation of 8T SRAM cell which is better than 6T SRAM cell using swing restoration for dual node voltage. New 8T SRAM technique on the circuit or architecture level is required. In this paper, comparative analysis of 6T and 8T SRAM cells with improved read and write margin is done for 130nm technology with cadence virtuoso schematics tool.

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Low Power March Memory Test Algorithm for Static Random Access Memories

International Journal of Engineering ◽

10.5829/ije.2018.31.02b.13 ◽

2018 ◽

Vol 31 (2) ◽

Cited By ~ 1

Keyword(s):

Low Power ◽

Random Access ◽

Memory Test ◽

Static Random Access Memories ◽

Test Algorithm

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Analysis of 6T SRAM Cell in Different Technologies

Circulation in Computer Science ◽

10.22632/ccs-2017-mcsp026 ◽

2017 ◽

Vol MCSP2017 (01) ◽

pp. 7-10 ◽

Cited By ~ 2

Author(s):

Subhashree Rath ◽

Siba Kumar Panda

Keyword(s):

Low Power ◽

Data Storage ◽

Low Voltage ◽

Random Access ◽

Storage Device ◽

Cmos Process ◽

Process Technology ◽

Digital Devices ◽

Noise Margin ◽

Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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