Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip

2015 ◽  
Author(s):  
Stephan Werner ◽  
Bernhard Stiehle ◽  
Jurgen Becker
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
System On Chip ◽  
Use Case ◽  
Cosine Transform ◽  
Case Comparison ◽  
On Chip

System on Chip Design for Multi-Principle of Relay Protection in the FPGA

2014 ◽  
Vol 668-669 ◽  
pp. 857-861
Author(s):  
Peng Fei Hu ◽  
Yu Xiang Yuan ◽  
Zhi Juan Qu ◽  
Xue Ping Jiang
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Relay Protection ◽  
Digital Signal ◽  
System On Chip ◽  
Process Scheduling ◽  
Chip Design ◽  
Protection Devices ◽  
On Chip ◽  
Set Up

To improve the reliability and integration of relay protection devices in power, the system on chip design for multi-principle of relay protection on FPGA is proposed. The data acquisition, digital signal processing, hardware protection algorithm, FPGA and MCU process scheduling, MCU and peripheral devices communication are designed, the hardware compilation model is set up by QuartusII on FPGA, and the simulation and experimental verification are performed. The results show that the proposed system can improve the speed of hardware protection and reduce the volume of the device, and has reconstruction on architecture.

scholarly journals Design of on-chip temperature-based digital signal processing for customized wireless microcontroller

2019 ◽  
Vol 14 (2) ◽  
pp. 653
Author(s):  
S.F. R. Faezal ◽  
M. N. Isa ◽  
S. Taking ◽  
S. N. Mohyar ◽  
A. B. Jambek ◽  
...  
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
System On Chip ◽  
Processing Unit ◽  
Verilog Hdl ◽  
Chip Design ◽  
Chip Area ◽  
Monitoring Process ◽  
On Chip

<span>Dramatic rises in power density and die sizes inside system-on-chip (SoC) design have led to the thermal issue. High temperatures or uneven temperature distributions may result not only in reliability issues, also has become the biggest issue that can limit the system performance.  This paper presents the design and simulation of a temperature-based digital signal processing unit for modern system-on-chip design using the Verilog HDL. This design provides continuous monitoring of temperature and reacts to specified conditions. The simulation of the system has been done on Synopsys Software. The result showed that temperature monitoring process is within the temperature range due to the incorporation of an interrupt-based system and with an advantage of minimum chip area required.</span>

Ultralow Power and Robust On-Chip Digital Signal Processing for Closed-Loop Neuro-Prosthesis

2014 ◽  
pp. 155-193
Author(s):  
Swarup Bhunia ◽  
Abhishek Basak ◽  
Seetharam Narasimhan ◽  
Maryam Sadat Hashemian
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Closed Loop ◽  
Digital Signal ◽  
Ultralow Power ◽  
On Chip

scholarly journals OPEN CORES FOR DIGITAL SIGNAL PROCESSING

2014 ◽  
Vol 25 (1) ◽  
pp. 53-62
Author(s):  
Juan Camilo Valderrama-Cuervo ◽  
Alexander López-Parrado
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Impulse Response ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Hardware Verification ◽  
Infinite Impulse Response ◽  
Iir Filter ◽  
On Chip

This paper presents the design and implementation of three System-on-Chip (SoC) cores, which implement the Digital Signal Processing (DSP) functions: Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter and Fast Fourier Transform (FFT). The FIR-filter core is based on the symmetrical realization form, the IIRfilter core is based on the Second Order Sections (SOS) architecture and the FFT core is based on the Radix 22 Single Delay Feedback (R22SDF) architecture. The three cores are compatible with the Wishbone SoC bus, and they were described using generic and structural VHDL. In-system hardware verification was performed by using an OpenRisc-based SoC synthesized on an Altera FPGA. Tests showed that the designed DSP cores are suitable for building SoC based on the OpenRisc processor and the Wishbone bus.

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