Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

2011 ◽  
Author(s):  
A Strano ◽  
C Gómez ◽  
D Ludovici ◽  
M Favalli ◽  
M E Gómez ◽  
...  
Keyword(s):  
Network On Chip ◽  
Structural Redundancy ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip ◽  
Test Architecture

A Mixed-Voltage Sensor Readout Circuit With On-Chip Calibration and Built-In Self-Test

2007 ◽  
Vol 7 (9) ◽  
pp. 1225-1232 ◽  
Author(s):  
Andrew Mason ◽  
Abhijeet V. Chavan ◽  
Kensall D. Wise
Keyword(s):  
Voltage Sensor ◽  
Readout Circuit ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip

scholarly journals Measuring Static Parameters of Embedded ADC Core

2011 ◽  
Vol 62 (2) ◽  
pp. 80-86
Author(s):  
Franc Novak ◽  
Peter Mrak ◽  
Anton Biasizzo
Keyword(s):  
Feasibility Study ◽  
Theoretical Background ◽  
System On Chip ◽  
Test Time ◽  
Hardware Overhead ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip ◽  
The Impact ◽  
Minimal Hardware

Measuring Static Parameters of Embedded ADC CoreThe paper presents the results of a feasibility study of measuring static parameters of ADC cores embedded in a System-on-Chip. Histogram based technique is employed because it is suitable for built-in self-test. While the theoretical background of the technique has been covered by numerous papers, less attention has been given to implementations in practice. Our goal was the implementation of histogram test in a IEEE Std 1500 wrapper. Two different solutions pursuing either minimal test time or minimal hardware overhead are described. The impact of MOS switches at ADC input on the performed measurements was considered.

Automatic generation of memory built-in self-test cores for system-on-chip

2002 ◽  
Author(s):  
Kuo-Liang Cheng ◽  
Chia-Ming Hsueh ◽  
Jing-Reng Huang ◽  
Jen-Chieh Yeh ◽  
Chih-Tsun Huang ◽  
...  
Keyword(s):  
Automatic Generation ◽  
System On Chip ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip
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