Design of quantum cost efficient 4-bit reversible universal shift register

2017 ◽  
Author(s):  
Heranmoy Maity ◽  
Arindam Biswas ◽  
Anup Kr. Bhattacherjee ◽  
Anita Pal
Keyword(s):  
Shift Register ◽  
Quantum Cost ◽  
Universal Shift Register ◽  
Cost Efficient

Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

2018 ◽  
Vol 16 (02) ◽  
pp. 1850016 ◽  
Author(s):  
H. Maity ◽  
A. Biswas ◽  
A. K. Bhattacharjee ◽  
A. Pal
Keyword(s):  
Quantum Computing ◽  
Logic Gate ◽  
Logic Gates ◽  
Reversible Logic ◽  
Shift Register ◽  
Optimized Design ◽  
Quantum Cost ◽  
Universal Shift Register ◽  
Reversible Logic Gates

In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

A novel QCA implementation of MUX-based universal shift register

2013 ◽  
Vol 13 (1) ◽  
pp. 198-210 ◽  
Author(s):  
Reza Sabbaghi-Nadooshan ◽  
Moein Kianpour
Keyword(s):  
Shift Register ◽  
Universal Shift Register

scholarly journals Analysis and Design of Universal Shift Register Using Pulsed Latches

2019 ◽  
Vol 8 (03) ◽  
pp. 10-16
Author(s):  
Mr. Dharmesh Dhabliya, Dr.S.A.Sivakumar
Keyword(s):  
Normal Force ◽  
Shift Register ◽  
Clock Rate ◽  
Analysis And Design ◽  
Low Level ◽  
Universal Shift Register

Power utilization and die region space are the significant boundaries which are considered for structuring low level power outcomes. This paper put forward the structure of low force general move register and 4-piece counter utilizing pipe rationale. Since flip failures are an innate structure hinder in a few applications, different flip lemon are over viewed and executed in widespread move register and 4-piece counter. Flip lemon utilizing pipe rationale is viewed as dependent on the correlation of intensity and region. At last, a low force all inclusive move register and 4-piece counter is planned utilizing pipe rationale. The proposed USR and 4-piece counters are mimicked with various clock rate going from 100 KHz to 500MHz. Re-enactment of these flip flounders, the widespread move register and the 4-piece counters are finished utilizing Tanner device at 180nm innovation. The normal force and the PDP of USR are improved by 33% and 27% and further the normal force and the PDP of 4-piece counter are improved by 36.9% and 30.2% when contrasted and existing plan separately. So the put forward plan is reasonable for low level power and elite applications.

scholarly journals Designing and Implementation of Efficient (2i x j) Reversible RAM-Array Module

2018 ◽  
Vol 7 (3.12) ◽  
pp. 808
Author(s):  
Srija Alla ◽  
Bharathi S H
Keyword(s):  
Power Dissipation ◽  
Vlsi Design ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Worst Case ◽  
Nano Technology ◽  
Flip Flop ◽  
Digital World ◽  
Reversible Gate ◽  
Cost Efficient

In the modern digital-world, power dissipation in microprocessors is becoming a significant challenge for the researchers to design an efficient reversible logic circuit. Thus, study on reversible logic design has been rapidly increased in present days for its application in Nano technology as well as in low energized VLSI design etc. In this current study, have realized a QC (i.e. quantum-cost) efficient (2i x j) reversible RAM array module with (3 x 3) New Modified Fredkin (NMF) reversible gate. Additionally, have introduced a Reversible D-Flip-Flop (RDFF) with less QC, and Reversible (i x 2i) decoder which produces the effective results in terms of QC and garbage-outputs. Finally, the study analyzed the designed architecture in terms of worst case delay.  

Design of Quantum Cost and Delay Optimized Code Converter Using New Reversible Quantum Circuit Block (QCB)

2020 ◽  
Vol 12 ◽  
Author(s):  
Heranmoy Maity ◽  
Sudipta Banerjee ◽  
Raton Mistry ◽  
Parna Kundu ◽  
Kriti Ojha ◽  
...  
Keyword(s):  
Quantum Circuit ◽  
Quantum Cost ◽  
Constant Input ◽  
Code Converter ◽  
Garbage Output ◽  
Feynman Gate ◽  
Cost Efficient ◽  
Optimized Code ◽  
Logic Functions ◽  
Very High

Background: In this article, we have proposed a new reversible quantum circuit block along with the quantum cost (QC), constant input (CI), garbage output (GO) and delay optimized code converterusing quantum circuit block. Method: Initially, new quantum circuit block has been designed and later reversible code converter circuits have been implemented using it. The proposed new quantum blockused to design 2’s complement code converter (2SCCC), cost efficient BCD to Excess-3 code converter (BECC) and can also be used to implement different logic functions. The QC of proposed quantum circuit block is 8. The QC and delay of the proposed 2SCCC is 8 and 1 respectively. Similarly, the QC and delay of the proposed BECC is 11 and 2 respectively. The proposed cost efficient BECC is designed using two NOT gate, one Feynman gate and one new quantum circuit block with QC is 11. Results: The improvement of QC for 2SCCC and BECC are 27.27 % and 21.43% respectively. The improvement of delay for 2SCCC and BECC are 66.67% and 50% respectively compared with respect to the latest reported results. Conclusion: So the improvement of QC and delay are very high using QCB.

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