ESD Co-Design ofmm-Wave RF Switch in 22nm SOI

Author(s):  
Feilong Zhang ◽  
Cheng Li ◽  
Mengfu Di ◽  
Zijin Pan ◽  
Han Wang ◽  
...  
Keyword(s):  
Author(s):  
Frédéric Drillet ◽  
Jérôme Loraine ◽  
Hassan Saleh ◽  
Imene Lahbib ◽  
Brice Grandchamp ◽  
...  

Abstract This paper presents the radio frequency (RF) measurements of an SPST switch realized in gallium nitride (GaN)/RF-SOI technology compared to its GaN/silicon (Si) equivalent. The samples are built with an innovative 3D heterogeneous integration technique. The RF switch transistors are GaN-based and the substrate is RF-SOI. The insertion loss obtained is below 0.4 dB up to 30 GHz while being 1 dB lower than its GaN/Si equivalent. This difference comes from the vertical capacitive coupling reduction of the transistor to the substrate. This reduction is estimated to 59% based on a RC network model fitted to S-parameters measurements. In large signal, the linearity study of the substrate through coplanar waveguide transmission line characterization shows the reduction of the average power level of H2 and H3 of 30 dB up to 38 dBm of input power. The large signal characterization of the SPST shows no compression up to 38 dBm and the H2 and H3 rejection levels at 38 dBm are respectively, 68 and 75 dBc.


2013 ◽  
Vol 34 (10) ◽  
pp. 1313-1315 ◽  
Author(s):  
Nabil El-Hinnawy ◽  
Pavel Borodulin ◽  
Brian Wagner ◽  
Matthew R. King ◽  
John S. Mason ◽  
...  

Author(s):  
Dandan Xia ◽  
Jianqiang Li ◽  
Chunjing Yin ◽  
Qiang Lv ◽  
Bingyu Li ◽  
...  

2019 ◽  
Vol 40 (2) ◽  
pp. 022401
Author(s):  
Hong Guan ◽  
Hao Sun ◽  
Junlin Bao ◽  
Zhipeng Wang ◽  
Shuguang Zhou ◽  
...  
Keyword(s):  

Circuit World ◽  
2019 ◽  
Vol 45 (2) ◽  
pp. 53-64
Author(s):  
Alireza Ardehshiri ◽  
Gholamreza Karimi ◽  
Ramin Dehdasht-Heydari

Purpose This paper aims to design, optimize and simulate the Radio Frequency (RF) micro electromechanical system (MEMS) Switch which is stimulated by electrostatically voltage. Design/methodology/approach The geometric structure of the switch was extracted based on the design of Taguchi-based experiment using the mathematical programming and obtaining objective function by the genetic meta-heuristic algorithm. Findings The RF parameters of the switch were calculated for the design of Taguchi-based S11 = −5.649 dB and S21 = −46.428 dB at the working frequency of 40 GHz. The pull-in voltage of the switch was 2.8 V and the axial residual stress of the proposed design was obtained 28 MPa and the design of Taguchi-based S11 = −4.422 dB and S21 = −48.705dB at the working frequency of 40 GHz. The pull-in voltage of the switch was 2.5 V and the axial residual stress of the proposed design was obtained 25 MPa. Originality/value A novel complex strategy in the design and optimization of capacitive RF switch MEMS modeling is proposed.


Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 507
Author(s):  
Behnam S. Rikan ◽  
David Kim ◽  
Kyung-Duk Choi ◽  
Arash Hejazi ◽  
Joon-Mo Yoo ◽  
...  

This paper presents a fast-switching Transmit/Receive (T/R) Single-Pole-Double-Throw (SPDT) Radio Frequency (RF) switch. Thorough analyses have been conducted to choose the optimum number of stacks, transistor sizes, gate and body voltages, to satisfy the required specifications. This switch applies six stacks of series and shunt transistors as big as 3.9 mm/160 nm and 0.75 mm/160 nm, respectively. A negative charge pump and a voltage booster generate the negative and boosted control voltages to improve the harmonics and to keep Inter-Modulation Distortion (IMD) performance of the switch over 100 dBc. A Low Drop-Out (LDO) regulator limits the boosted voltage in Absolute Maximum Rating (AMR) conditions and improves the switch performance for Process, Voltage and Temperature (PVT) variations. To reduce the size, a dense custom-made capacitor consisting of different types of capacitors has been presented where they have been placed over each other in layout considering the Design Rule Checks (DRC) and applied in negative charge pump, voltage booster and LDO. This switch has been fabricated and tested in a 90 nm Silicon-on-Insulator (SOI) process. The second and third IMD for all specified blockers remain over 100 dBc and the switching time as fast as 150 ns has been achieved. The Insertion Loss (IL) and isolation at 2.7 GHz are −0.17 dB and −33 dB, respectively. This design consumes 145 uA from supply voltage range of 1.65 V to 1.95 V and occupies 440 × 472 µm2 of die area.


2009 ◽  
Vol 45 (4) ◽  
pp. 207 ◽  
Author(s):  
G. Simin ◽  
A. Koudymov ◽  
Z. Yang ◽  
X. Hu ◽  
J. Yang ◽  
...  
Keyword(s):  

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